mirror of https://github.com/YosysHQ/abc.git
silence clang errors when compiling as C++
This commit is contained in:
parent
8ee49ff150
commit
c0ba25a693
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@ -692,7 +692,7 @@ int Gia_ManEncodeFanin( Gia_Man_t * p, int iLit )
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// return iANDp;
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}
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// find fanout code
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int Gia_ManEncodeFanout( Gia_Man_t * p, Gia_Obj_t * pObj, int i )
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Gia_ObjType_t Gia_ManEncodeFanout( Gia_Man_t * p, Gia_Obj_t * pObj, int i )
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{
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// int iLit;
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if ( Gia_ObjIsPo(p, pObj) )
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@ -869,7 +869,7 @@ extern ABC_DLL int Abc_NtkRewrite( Abc_Ntk_t * pNtk, int fUpdateL
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extern ABC_DLL int Abc_NtkMiterSat( Abc_Ntk_t * pNtk, ABC_INT64_T nConfLimit, ABC_INT64_T nInsLimit, int fVerbose, ABC_INT64_T * pNumConfs, ABC_INT64_T * pNumInspects );
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extern ABC_DLL void * Abc_NtkMiterSatCreate( Abc_Ntk_t * pNtk, int fAllPrimes );
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/*=== abcSop.c ==========================================================*/
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extern ABC_DLL char * Abc_SopRegister( Mem_Flex_t * pMan, char * pName );
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extern ABC_DLL char * Abc_SopRegister( Mem_Flex_t * pMan, const char * pName );
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extern ABC_DLL char * Abc_SopStart( Mem_Flex_t * pMan, int nCubes, int nVars );
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extern ABC_DLL char * Abc_SopCreateConst0( Mem_Flex_t * pMan );
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extern ABC_DLL char * Abc_SopCreateConst1( Mem_Flex_t * pMan );
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@ -53,7 +53,7 @@ ABC_NAMESPACE_IMPL_START
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SeeAlso []
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***********************************************************************/
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char * Abc_SopRegister( Mem_Flex_t * pMan, char * pName )
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char * Abc_SopRegister( Mem_Flex_t * pMan, const char * pName )
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{
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char * pRegName;
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if ( pName == NULL ) return NULL;
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@ -110,7 +110,7 @@ static void Psr_ManWriteVerilogBoxes( FILE * pFile, Psr_Ntk_t * p )
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Vec_Int_t * vBox; int i;
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Psr_NtkForEachBox( p, vBox, i )
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{
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Bac_ObjType_t NtkId = Psr_BoxNtk(p, i);
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Bac_ObjType_t NtkId = (Bac_ObjType_t)Psr_BoxNtk(p, i);
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if ( NtkId == BAC_BOX_MUX )
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Psr_ManWriteVerilogMux( pFile, p, vBox );
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else if ( Psr_BoxIsNode(p, i) ) // node ------- check order of fanins
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@ -90,7 +90,8 @@ void Cba_NtkPrintDistrib( Cba_Ntk_t * p, int fVerbose )
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Vec_Ptr_t * vTypes, * vOccurs;
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Vec_Int_t * vAnds = Vec_IntStart( CBA_BOX_LAST );
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int iRnObj = -1, nCountRange = 0;
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int i, k, s, s0, s1, Type; word Sign;
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int i, k, s, s0, s1; word Sign;
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Cba_ObjType_t Type;
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char * pTypeNames[CBA_BOX_LAST];
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Cba_ManCreatePrimMap( pTypeNames );
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// allocate statistics arrays
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@ -1060,7 +1061,7 @@ Cba_Man_t * Cba_ManDeriveFromGia( Gia_Man_t * pGia, int fUseXor )
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Cba_NtkCleanObjNames( pNtk );
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Gia_ManForEachCiId( pGia, iObj, i )
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{
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NameId = pGia->vNamesIn? Abc_NamStrFindOrAdd(p->pStrs, Vec_PtrEntry(pGia->vNamesIn, i), NULL) : Cba_NtkNewStrId(pNtk, "i%d", i);
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NameId = pGia->vNamesIn? Abc_NamStrFindOrAdd(p->pStrs, (char*)Vec_PtrEntry(pGia->vNamesIn, i), NULL) : Cba_NtkNewStrId(pNtk, "i%d", i);
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iObjNew = Cba_ObjAlloc( pNtk, CBA_OBJ_PI, 0, 1 );
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Cba_ObjSetName( pNtk, iObjNew, NameId );
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Vec_IntWriteEntry( vLit2Fon, Abc_Var2Lit(iObj, 0), Cba_ObjFon0(pNtk, iObjNew) );
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@ -1082,7 +1083,7 @@ Cba_Man_t * Cba_ManDeriveFromGia( Gia_Man_t * pGia, int fUseXor )
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iObjNew = Cba_ObjAlloc( pNtk, CBA_BOX_BUF, 1, 1 );
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Cba_ObjSetFinFon( pNtk, iObjNew, 0, iFon0 );
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iFon0 = Cba_ObjFon0(pNtk, iObjNew); // non-const fon unique for this output
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NameId = pGia->vNamesOut? Abc_NamStrFindOrAdd(p->pStrs, Vec_PtrEntry(pGia->vNamesOut, i), NULL) : Cba_NtkNewStrId(pNtk, "o%d", i);
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NameId = pGia->vNamesOut? Abc_NamStrFindOrAdd(p->pStrs, (char*)Vec_PtrEntry(pGia->vNamesOut, i), NULL) : Cba_NtkNewStrId(pNtk, "o%d", i);
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iObjNew = Cba_ObjAlloc( pNtk, CBA_OBJ_PO, 1, 0 );
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Cba_ObjSetName( pNtk, iObjNew, NameId );
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Cba_ObjSetFinFon( pNtk, iObjNew, 0, iFon0 );
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@ -1879,7 +1879,7 @@ int Prs_CreateVerilogNtk( Cba_Ntk_t * p, Prs_Ntk_t * pNtk )
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if ( Prs_BoxIsNode(pNtk, i) ) // node
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{
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Type = Prs_BoxNtk(pNtk, i);
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iObj = Cba_ObjAlloc( p, Type, Prs_BoxIONum(pNtk, i)-1, Type == CBA_BOX_ADD ? 2 : 1 );
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iObj = Cba_ObjAlloc( p, (Cba_ObjType_t)Type, Prs_BoxIONum(pNtk, i)-1, Type == CBA_BOX_ADD ? 2 : 1 );
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Prs_CreateSignalOut( p, Cba_ObjFon0(p, iObj), pNtk, Vec_IntEntry(vBox, 1) ); // node output
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}
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else // box
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@ -1921,7 +1921,7 @@ int Prs_CreateVerilogNtk( Cba_Ntk_t * p, Prs_Ntk_t * pNtk )
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else if ( (Type == CBA_BOX_DFFRS || Type == CBA_BOX_LATCHRS) && !strncmp(pNtkName, "wide_", strlen("wide_")) && !Prs_CreateFlopSetReset(p, pNtk, vBox, NULL, NULL, NULL, NULL) )
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nInputs = atoi(pNtkName+strlen(Type == CBA_BOX_DFFRS ? "wide_dffrs_" : "wide_latchrs_")), nOutputs = 1, Type = CBA_BOX_CONCAT;
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// create object
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iObj = Cba_ObjAlloc( p, Type, nInputs, nOutputs );
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iObj = Cba_ObjAlloc( p, (Cba_ObjType_t)Type, nInputs, nOutputs );
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if ( pBox ) Cba_ObjSetFunc( p, iObj, Cba_NtkId(pBox) );
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// mark PO objects
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Cba_NtkCleanMap2( p );
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@ -2002,7 +2002,7 @@ int Prs_CreateVerilogNtk( Cba_Ntk_t * p, Prs_Ntk_t * pNtk )
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for ( w = 0; w < Width; w++ )
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{
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// create bit-level flop
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int iObjNew = Cba_ObjAlloc( p, Type, 4, 1 );
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int iObjNew = Cba_ObjAlloc( p, (Cba_ObjType_t)Type, 4, 1 );
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if ( Prs_BoxName(pNtk, i) )
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{
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NameId = Cba_NtkNewStrId( p, "%s[%d]", Prs_NtkStr(pNtk, Prs_BoxName(pNtk, i)), w );
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@ -233,7 +233,7 @@ static void Prs_ManWriteVerilogBoxes( FILE * pFile, Prs_Ntk_t * p, char ** pType
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Vec_Int_t * vBox; int i, k;
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Prs_NtkForEachBox( p, vBox, i )
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{
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Cba_ObjType_t NtkId = Prs_BoxNtk(p, i);
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Cba_ObjType_t NtkId = (Cba_ObjType_t)Prs_BoxNtk(p, i);
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//char * pNtkName = Prs_ObjGetName(p, Prs_BoxName(p, i));
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if ( NtkId == CBA_BOX_MUX && Prs_BoxIsNode(p, i) )
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Prs_ManWriteVerilogMux( pFile, p, vBox );
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@ -918,7 +918,7 @@ void Cba_ManWriteVerilogNtk( Cba_Ntk_t * p, int fInlineConcat )
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Vec_StrPush( vStr, ' ' );
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Cba_ManWriteFonName( p, Cba_ObjFinFon(p, iObj, 2), fInlineConcat, 0 );
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}
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else if ( Cba_TypeIsUnary(Type) )
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else if ( Cba_TypeIsUnary((Cba_ObjType_t)Type) )
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{
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Vec_StrPrintStr( vStr, Cba_NtkTypeName(p, Type) );
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Cba_ManWriteFonName( p, Cba_ObjFinFon(p, iObj, 0), fInlineConcat, 0 );
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@ -444,13 +444,13 @@ int Extra_ThreshAssignWeights(word * t, char * pIsop, char * pIsopFneg,
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unsigned long **pGreaters;
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unsigned long **pSmallers;
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pGreaters = malloc(nCubesIsop * nCubesIsopFneg * sizeof *pGreaters);
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pGreaters = (unsigned long **)malloc(nCubesIsop * nCubesIsopFneg * sizeof *pGreaters);
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for (i = 0; i < nCubesIsop * nCubesIsopFneg; i++) {
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pGreaters[i] = malloc(nChows * sizeof *pGreaters[i]);
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pGreaters[i] = (unsigned long *)malloc(nChows * sizeof *pGreaters[i]);
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}
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pSmallers = malloc(nCubesIsop * nCubesIsopFneg * sizeof *pSmallers);
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pSmallers = (unsigned long **)malloc(nCubesIsop * nCubesIsopFneg * sizeof *pSmallers);
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for (i = 0; i < nCubesIsop * nCubesIsopFneg; i++) {
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pSmallers[i] = malloc(nChows * sizeof *pSmallers[i]);
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pSmallers[i] = (unsigned long *)malloc(nChows * sizeof *pSmallers[i]);
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}
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//******************************
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@ -236,7 +236,7 @@ static inline int Scl_ConHasInLoads_( Scl_Con_t * p ) { return Vec_Wrd
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static inline int Scl_ConHasOutReqs_( Scl_Con_t * p ) { return Vec_WrdCountZero(&p->vOutReqs) != Vec_WrdSize(&p->vOutReqs); }
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static inline int Scl_ConHasOutLoads_( Scl_Con_t * p ) { return Vec_WrdCountZero(&p->vOutLoads) != Vec_WrdSize(&p->vOutLoads); }
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static inline char * Scl_ConGetInCell_( Scl_Con_t * p, int i ) { return Vec_PtrEntry( &p->vInCells, i ); }
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static inline char * Scl_ConGetInCell_( Scl_Con_t * p, int i ) { return (char*)Vec_PtrEntry( &p->vInCells, i ); }
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static inline word Scl_ConGetInArr_( Scl_Con_t * p, int i ) { return Vec_WrdEntry( &p->vInArrs, i ); }
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static inline word Scl_ConGetInSlew_( Scl_Con_t * p, int i ) { return Vec_WrdEntry( &p->vInSlews, i ); }
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static inline word Scl_ConGetInLoad_( Scl_Con_t * p, int i ) { return Vec_WrdEntry( &p->vInLoads, i ); }
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@ -295,10 +295,10 @@ void Abc_FlowRetime_SimulateNode( Abc_Obj_t * pObj ) {
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Abc_Obj_t * pFanin;
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int i, rAnd, rVar, dcAnd, dcVar;
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#ifdef ABC_USE_CUDD
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DdManager * dd = pNtk->pManFunc;
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DdNode *pBdd = pObj->pData, *pVar;
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DdManager * dd = (DdManager*)pNtk->pManFunc;
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DdNode *pBdd = (DdNode*)pObj->pData, *pVar;
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#endif
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Hop_Man_t *pHop = pNtk->pManFunc;
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Hop_Man_t *pHop = (Hop_Man_t*)pNtk->pManFunc;
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assert(!Abc_ObjIsLatch(pObj));
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assert(Abc_ObjRegular(pObj));
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@ -376,7 +376,7 @@ void Abc_FlowRetime_SimulateNode( Abc_Obj_t * pObj ) {
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Hop_ManPi(pHop, i)->fMarkB = FTEST(pFanin, INIT_CARE)?1:0;
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}
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Abc_FlowRetime_EvalHop_rec( pHop, pObj->pData, &rVar, &dcVar );
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Abc_FlowRetime_EvalHop_rec( pHop, (Hop_Obj_t*)pObj->pData, &rVar, &dcVar );
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Abc_FlowRetime_SetInitValue(pObj, rVar, dcVar);
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@ -415,7 +415,7 @@ void Abc_FlowRetime_SimulateNode( Abc_Obj_t * pObj ) {
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// ------ MAPPED network
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else if ( Abc_NtkHasMapping( pNtk )) {
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Abc_FlowRetime_SimulateSop( pObj, (char *)Mio_GateReadSop(pObj->pData) );
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Abc_FlowRetime_SimulateSop( pObj, (char *)Mio_GateReadSop((Mio_Gate_t*)pObj->pData) );
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return;
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}
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@ -622,7 +622,7 @@ int Abc_FlowRetime_SolveBackwardInit( Abc_Ntk_t * pNtk ) {
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// clear initial values, associate PIs to latches
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Abc_NtkForEachPi( pManMR->pInitNtk, pInitObj, i ) Abc_ObjSetCopy( pInitObj, NULL );
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Abc_NtkForEachLatch( pNtk, pObj, i ) {
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pInitObj = Abc_ObjData( pObj );
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pInitObj = (Abc_Obj_t*)Abc_ObjData( pObj );
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assert( Abc_ObjIsPi( pInitObj ));
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Abc_ObjSetCopy( pInitObj, pObj );
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Abc_LatchSetInitNone( pObj );
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@ -699,7 +699,7 @@ void Abc_FlowRetime_UpdateBackwardInit( Abc_Ntk_t * pNtk ) {
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// add PIs to to latches
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Abc_NtkForEachLatch( pNtk, pOrigObj, i ) {
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assert(Vec_PtrSize(vPi) > 0);
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pInitObj = Vec_PtrPop(vPi);
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pInitObj = (Abc_Obj_t*)Vec_PtrPop(vPi);
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// DEBUG
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// printf("update : mapping latch %d to PI %d\n", pOrigObj->Id, pInitObj->Id);
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@ -773,7 +773,7 @@ Abc_Obj_t *Abc_FlowRetime_CopyNodeToInitNtk( Abc_Obj_t *pOrigObj ) {
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pData = Abc_SopCreateAnd( (Mem_Flex_t *)pInitNtk->pManFunc, 2, fCompl );
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assert(pData);
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pInitObj->pData = Abc_SopRegister( (Mem_Flex_t *)pInitNtk->pManFunc, pData );
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pInitObj->pData = Abc_SopRegister( (Mem_Flex_t *)pInitNtk->pManFunc, (const char*)pData );
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}
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// (ii) mapped node -> SOP node
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@ -787,11 +787,11 @@ Abc_Obj_t *Abc_FlowRetime_CopyNodeToInitNtk( Abc_Obj_t *pOrigObj ) {
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return pInitObj;
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}
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pInitObj = Abc_NtkCreateObj( pInitNtk, Abc_ObjType(pOrigObj) );
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pData = Mio_GateReadSop(pOrigObj->pData);
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assert( Abc_SopGetVarNum(pData) == Abc_ObjFaninNum(pOrigObj) );
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pInitObj = Abc_NtkCreateObj( pInitNtk, (Abc_ObjType_t)Abc_ObjType(pOrigObj) );
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pData = Mio_GateReadSop((Mio_Gate_t*)pOrigObj->pData);
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assert( Abc_SopGetVarNum((char*)pData) == Abc_ObjFaninNum(pOrigObj) );
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pInitObj->pData = Abc_SopRegister( (Mem_Flex_t *)pInitNtk->pManFunc, pData );
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pInitObj->pData = Abc_SopRegister( (Mem_Flex_t *)pInitNtk->pManFunc, (const char*)pData );
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}
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// (iii) otherwise, duplicate obj
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@ -1069,7 +1069,7 @@ void Abc_FlowRetime_ConstrainInit( ) {
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#endif
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// mark its TFO
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pObj = Vec_PtrEntry( vNodes, low );
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pObj = (Abc_Obj_t*)Vec_PtrEntry( vNodes, low );
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Abc_NtkMarkCone_rec( pObj, 1 );
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vprintf(" conflict term = %d ", low);
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@ -1170,7 +1170,7 @@ static void Abc_FlowRetime_ConnectBiasNode(Abc_Obj_t *pBiasNode, Abc_Obj_t *pObj
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Abc_NtkIncrementTravId( pNtk );
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while (Vec_PtrSize( vNodes )) {
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pCur = Vec_PtrPop( vNodes );
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pCur = (Abc_Obj_t*)Vec_PtrPop( vNodes );
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lag = Vec_IntPop( vLags );
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if (Abc_NodeIsTravIdCurrent( pCur )) continue;
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@ -1262,7 +1262,7 @@ void Abc_FlowRetime_ClearInitToOrig( Abc_Obj_t *pInit )
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if (id >= pManMR->sizeInitToOrig) {
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int oldSize = pManMR->sizeInitToOrig;
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pManMR->sizeInitToOrig = 1.5*id + 10;
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pManMR->pInitToOrig = realloc(pManMR->pInitToOrig, sizeof(NodeLag_t)*pManMR->sizeInitToOrig);
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pManMR->pInitToOrig = (NodeLag_t*)realloc(pManMR->pInitToOrig, sizeof(NodeLag_t)*pManMR->sizeInitToOrig);
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memset( &(pManMR->pInitToOrig[oldSize]), 0, sizeof(NodeLag_t)*(pManMR->sizeInitToOrig-oldSize) );
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}
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assert( pManMR->pInitToOrig );
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@ -1291,7 +1291,7 @@ void Abc_FlowRetime_SetInitToOrig( Abc_Obj_t *pInit, Abc_Obj_t *pOrig)
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if (id >= pManMR->sizeInitToOrig) {
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int oldSize = pManMR->sizeInitToOrig;
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pManMR->sizeInitToOrig = 1.5*id + 10;
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pManMR->pInitToOrig = realloc(pManMR->pInitToOrig, sizeof(NodeLag_t)*pManMR->sizeInitToOrig);
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pManMR->pInitToOrig = (NodeLag_t*)realloc(pManMR->pInitToOrig, sizeof(NodeLag_t)*pManMR->sizeInitToOrig);
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memset( &(pManMR->pInitToOrig[oldSize]), 0, sizeof(NodeLag_t)*(pManMR->sizeInitToOrig-oldSize) );
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}
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assert( pManMR->pInitToOrig );
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@ -188,7 +188,7 @@ Abc_FlowRetime_MinReg( Abc_Ntk_t * pNtk, int fVerbose,
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if (pManMR->vSinkDistHist) Vec_IntFree(pManMR->vSinkDistHist);
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if (pManMR->maxDelay) Abc_FlowRetime_FreeTiming( pNtk );
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while( Vec_PtrSize( pManMR->vInitConstraints )) {
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pData = Vec_PtrPop( pManMR->vInitConstraints );
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pData = (InitConstraint_t*)Vec_PtrPop( pManMR->vInitConstraints );
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//assert( pData->pBiasNode );
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//Abc_NtkDeleteObj( pData->pBiasNode );
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ABC_FREE( pData->vNodes.pArray );
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@ -791,7 +791,7 @@ Abc_FlowRetime_CopyInitState( Abc_Obj_t * pSrc, Abc_Obj_t * pDest ) {
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}
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if (!pManMR->fIsForward) {
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pObj = Abc_ObjData(pSrc);
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pObj = (Abc_Obj_t*)Abc_ObjData(pSrc);
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assert(Abc_ObjIsPi(pObj));
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FDATA(pDest)->pInitObj = pObj;
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}
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@ -1373,7 +1373,7 @@ void Abc_ObjPrintNeighborhood( Abc_Obj_t *pObj, int depth ) {
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Abc_ObjPrintNeighborhood_rec( pObj, vNodes, depth );
|
||||
|
||||
while(Vec_PtrSize(vNodes)) {
|
||||
pObj2 = Vec_PtrPop(vNodes);
|
||||
pObj2 = (Abc_Obj_t*)Vec_PtrPop(vNodes);
|
||||
pObj2->fMarkC = 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ void Abc_FlowRetime_ConstrainConserv( Abc_Ntk_t * pNtk ) {
|
|||
// clear all exact constraints
|
||||
pManMR->nExactConstraints = 0;
|
||||
while( Vec_PtrSize( pManMR->vExactNodes )) {
|
||||
pObj = Vec_PtrPop( pManMR->vExactNodes );
|
||||
pObj = (Abc_Obj_t*)Vec_PtrPop( pManMR->vExactNodes );
|
||||
|
||||
if ( Vec_PtrSize( FTIMEEDGES(pObj) )) {
|
||||
pArray = Vec_PtrReleaseArray( FTIMEEDGES(pObj) );
|
||||
|
|
@ -619,7 +619,7 @@ void Abc_FlowRetime_FreeTiming( Abc_Ntk_t *pNtk ) {
|
|||
void *pArray;
|
||||
|
||||
while( Vec_PtrSize( pManMR->vExactNodes )) {
|
||||
pObj = Vec_PtrPop( pManMR->vExactNodes );
|
||||
pObj = (Abc_Obj_t*)Vec_PtrPop( pManMR->vExactNodes );
|
||||
|
||||
if ( Vec_PtrSize( FTIMEEDGES(pObj) )) {
|
||||
pArray = Vec_PtrReleaseArray( FTIMEEDGES(pObj) );
|
||||
|
|
|
|||
Loading…
Reference in New Issue