 Alan Mishchenko
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04be8af560
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Important bug fixes in standard-cell library handling and mapper &nf.
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2015-08-28 17:47:00 -07:00 |
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Alan Mishchenko
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77d64787e0
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Changes to be able to compile ABC without CUDD.
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2015-08-24 19:49:18 -07:00 |
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Alan Mishchenko
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1fffe8f6f3
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New switch in 'read_lib' to replace gate/pin names by short strings.
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2015-08-24 18:07:10 -07:00 |
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Alan Mishchenko
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5bf0f86450
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New switch in 'read_lib' to replace gate/pin names by short strings.
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2015-08-24 17:40:20 -07:00 |
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Alan Mishchenko
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0e4561ab9f
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Experiments with mapping plus small changes.
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2015-08-23 20:38:55 -07:00 |
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Alan Mishchenko
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10e0f3c58d
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Small changes to enable collecting results using &ps -D file.
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2015-07-09 11:50:24 -07:00 |
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Alan Mishchenko
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fd5b7e8b5d
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Bug fix in programmable cell parser and minor tuning.
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2015-07-08 16:59:22 -07:00 |
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Alan Mishchenko
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609be7a114
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C++ compiler typecast problem.
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2015-07-08 15:04:26 -07:00 |
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Alan Mishchenko
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9894fc762e
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Add fix to Liberty parser to skip extra semicolon.
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2015-07-06 07:57:18 -07:00 |
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Alan Mishchenko
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b4d0abb77d
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Undo recent assert.
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2015-06-27 21:38:32 -07:00 |
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Alan Mishchenko
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66ef4a9ac1
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Potential performance bug in the mapper.
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2015-06-27 19:57:49 -07:00 |
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Alan Mishchenko
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d0d7763ef8
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Supporting AND-gate cuts in 'if' and '&if'
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2015-06-21 13:31:02 -07:00 |
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Alan Mishchenko
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14b7a520a1
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Bug fix in 'dsd_tune' when processing cells with 0-input LUTs.
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2015-05-15 22:36:11 -07:00 |
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Alan Mishchenko
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37b6b5f1f8
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Making sure 0-input LUTs are supported by the DSD matching code.
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2015-05-14 13:12:17 -07:00 |
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Alan Mishchenko
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c0f0e145c4
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Improving the criteria to select representative gates in 'map' with floating-point-delay libraries having more than one gate in some functionality classes.
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2015-04-25 14:58:29 -07:00 |
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Alan Mishchenko
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9e20b3016d
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Adding switch 'map -f' to not use large gates for high-fanout nodes (disabled by default).
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2015-04-24 14:51:34 -07:00 |
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Alan Mishchenko
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a78fb767ee
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Adding platform-independent (alphabetic) way of sorting Genlib gates and selecting representatives based on area/delay.
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2015-04-17 21:02:15 +09:00 |
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Alan Mishchenko
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3de5d18c5f
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Adding APIs to retrieve NOR/OR gates from the library.
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2015-04-14 18:53:28 +09:00 |
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Alan Mishchenko
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b3e5ccd256
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Getting default AND-node delay from Genlib library.
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2015-04-06 10:56:14 +07:00 |
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Alan Mishchenko
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bb22a20cb0
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Support for representing programmable cell configuration data (bug fix).
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2015-03-09 08:36:22 -07:00 |
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Alan Mishchenko
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193c46e3c6
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Support for representing programmable cell configuration data.
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2015-03-08 20:19:56 -07:00 |
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Alan Mishchenko
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56f783157a
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Support for representing programmable cell configuration data.
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2015-03-08 20:17:59 -07:00 |
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Alan Mishchenko
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6da21b8b88
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Experiments with SAT-based cube enumeration.
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2015-03-05 23:00:30 -08:00 |
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Alan Mishchenko
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874d394089
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Corner case bug in wire-cap estimation.
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2015-02-18 09:18:01 -08:00 |
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Alan Mishchenko
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fd877c3f37
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Several improvements to CBA data-structure.
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2015-02-09 15:36:25 -08:00 |
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Alan Mishchenko
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68467cfff7
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Fixed a typo in variable names.
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2015-02-07 22:29:14 -08:00 |
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Alan Mishchenko
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8410daf3e4
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Improvements and tuning of CBA with buffering/sizing.
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2015-02-04 16:29:55 -08:00 |
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Alan Mishchenko
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7b1c25086b
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Improvements and tuning of CBA.
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2015-02-01 20:50:59 -08:00 |
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Alan Mishchenko
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77dbe2b656
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Major rehash of the CBA code.
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2015-01-31 19:52:32 -08:00 |
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Alan Mishchenko
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0f22046bcb
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New assertions and bug fix in DSD balancing.
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2015-01-27 09:54:35 -08:00 |
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Alan Mishchenko
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58d28539a7
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Gate sizing with barrier buffers.
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2014-12-21 22:22:31 -08:00 |
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Alan Mishchenko
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6733abd72e
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Exprimental features in tech-mapping.
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2014-12-21 01:04:39 -08:00 |
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Alan Mishchenko
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55f0a2805c
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Bug fix in reading box library.
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2014-12-20 10:16:13 -08:00 |
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Alan Mishchenko
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aadfea8b4d
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Integrating barrier buffers.
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2014-12-13 12:37:04 -08:00 |
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Alan Mishchenko
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b379b3ee20
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Adding new mapping feature.
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2014-12-11 20:45:41 -08:00 |
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Alan Mishchenko
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1398de7c46
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Integrating barrier buffers.
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2014-12-08 14:10:41 -08:00 |
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Alan Mishchenko
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3653bf53e9
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Bug fix in truth table computation.
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2014-10-15 14:26:44 -07:00 |
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Alan Mishchenko
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3ac8aa9c12
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Recommended changes for portability.
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2014-10-12 09:10:27 -07:00 |
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Alan Mishchenko
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8b160138f1
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MUX decomposition during mapping.
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2014-10-11 17:19:41 -07:00 |
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Alan Mishchenko
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09a5950c8f
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Deriving network in terms of programmable cells.
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2014-10-11 15:53:32 -07:00 |
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Alan Mishchenko
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ccb5bb34d7
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Suggested patch for type-punned warnings
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2014-10-10 08:58:18 -07:00 |
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Alan Mishchenko
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ca9eca3b22
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Small changes.
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2014-10-08 13:26:23 -07:00 |
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Alan Mishchenko
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141c1de0a2
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Compiler warnings.
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2014-10-08 10:52:32 -07:00 |
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Alan Mishchenko
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e4d5887671
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Detection of threshold functions.
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2014-10-08 10:41:20 -07:00 |
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Alan Mishchenko
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734435f441
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Deriving cell mapping with &if -kz.
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2014-10-04 19:36:41 -07:00 |
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Alan Mishchenko
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24083998ab
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Deriving cell mapping with &if -kz.
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2014-10-04 19:18:34 -07:00 |
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Alan Mishchenko
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fa5f05e3a2
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Deriving AIG after cell mapping.
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2014-10-03 17:15:43 -07:00 |
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Alan Mishchenko
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76666174b4
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Synchronizing packages.
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2014-09-20 16:41:11 -07:00 |
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Alan Mishchenko
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2d4342f8c4
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Synchronizing packages.
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2014-09-20 14:50:52 -07:00 |
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Alan Mishchenko
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00b8cda3d3
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Synchronizing packages.
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2014-09-20 14:10:05 -07:00 |
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