mirror of https://github.com/YosysHQ/abc.git
Corner case bug in wire-cap estimation.
This commit is contained in:
parent
525137926d
commit
874d394089
|
|
@ -56,6 +56,8 @@ Vec_Flt_t * Abc_SclFindWireCaps( SC_WireLoad * pWL, int nFanoutMax )
|
|||
vCaps = Vec_FltStart( Abc_MaxInt(nFanoutMax, EntryMax) + 1 );
|
||||
Vec_IntForEachEntry( pWL->vFanout, Entry, i )
|
||||
Vec_FltWriteEntry( vCaps, Entry, Vec_FltEntry(pWL->vLen, i) * pWL->cap );
|
||||
if ( Vec_FltEntry(vCaps, 1) == 0 )
|
||||
return vCaps;
|
||||
// interpolate between the values
|
||||
assert( Vec_FltEntry(vCaps, 1) != 0 );
|
||||
iPrev = 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue