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Getting default AND-node delay from Genlib library.

This commit is contained in:
Alan Mishchenko 2015-04-06 10:56:14 +07:00
parent c0c7723f1d
commit b3e5ccd256
4 changed files with 16 additions and 1 deletions
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2
src/base/abc/abcNtk.c
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@ -144,6 +144,8 @@ Abc_Ntk_t * Abc_NtkStartFrom( Abc_Ntk_t * pNtk, Abc_NtkType_t Type, Abc_NtkFunc_
if ( pNtk->vObjPerm )
pNtkNew->vObjPerm = Vec_IntDup( pNtk->vObjPerm );
pNtkNew->AndGateDelay = pNtk->AndGateDelay;
if ( pNtkNew->pManTime && Abc_FrameReadLibGen() && pNtkNew->AndGateDelay == 0.0 )
pNtkNew->AndGateDelay = Mio_LibraryReadDelayAigNode((Mio_Library_t *)Abc_FrameReadLibGen());
// initialize logic level of the CIs
if ( pNtk->AndGateDelay != 0.0 && pNtk->pManTime != NULL && pNtk->ntkType != ABC_NTK_STRASH && Type == ABC_NTK_STRASH )
{

13
src/base/abci/abcIf.c
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@ -23,6 +23,7 @@
#include "map/if/if.h"
#include "bool/kit/kit.h"
#include "aig/aig/aig.h"
#include "map/mio/mio.h"
ABC_NAMESPACE_IMPL_START
@ -115,9 +116,19 @@ Abc_Ntk_t * Abc_NtkIf( Abc_Ntk_t * pNtk, If_Par_t * pPars )
pPars->pTimesReq = Abc_NtkGetCoRequiredFloats(pNtk);
// update timing info to reflect logic level
if ( (pPars->fDelayOpt || pPars->fDsdBalance || pPars->fUserRecLib) && pNtk->AndGateDelay != 0.0 )
if ( (pPars->fDelayOpt || pPars->fDsdBalance || pPars->fUserRecLib) && pNtk->pManTime )
{
int c;
if ( pNtk->AndGateDelay == 0.0 )
{
if ( Abc_FrameReadLibGen() )
pNtk->AndGateDelay = Mio_LibraryReadDelayAigNode((Mio_Library_t *)Abc_FrameReadLibGen());
if ( pNtk->AndGateDelay == 0.0 )
{
pNtk->AndGateDelay = 1.0;
printf( "The AIG-node delay is not set. Assuming unit-delay.\n" );
}
}
for ( c = 0; c < Abc_NtkCiNum(pNtk); c++ )
pPars->pTimesArr[c] /= pNtk->AndGateDelay;
for ( c = 0; c < Abc_NtkCoNum(pNtk); c++ )

1
src/map/mio/mio.h
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@ -112,6 +112,7 @@ extern float Mio_LibraryReadDelayNand2Rise( Mio_Library_t * pLib );
extern float Mio_LibraryReadDelayNand2Fall( Mio_Library_t * pLib );
extern float Mio_LibraryReadDelayNand2Max( Mio_Library_t * pLib );
extern float Mio_LibraryReadDelayAnd2Max( Mio_Library_t * pLib );
extern float Mio_LibraryReadDelayAigNode( Mio_Library_t * pLib );
extern float Mio_LibraryReadAreaInv ( Mio_Library_t * pLib );
extern float Mio_LibraryReadAreaBuf ( Mio_Library_t * pLib );
extern float Mio_LibraryReadAreaNand2 ( Mio_Library_t * pLib );

1
src/map/mio/mioApi.c
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@ -57,6 +57,7 @@ float Mio_LibraryReadDelayNand2Rise( Mio_Library_t * pLib ) { retur
float Mio_LibraryReadDelayNand2Fall( Mio_Library_t * pLib ) { return (float)(pLib->pGateNand2? pLib->pGateNand2->pPins->dDelayBlockFall : 0.0); }
float Mio_LibraryReadDelayNand2Max ( Mio_Library_t * pLib ) { return (float)(pLib->pGateNand2? pLib->pGateNand2->pPins->dDelayBlockMax : 0.0); }
float Mio_LibraryReadDelayAnd2Max ( Mio_Library_t * pLib ) { return (float)(pLib->pGateAnd2? pLib->pGateAnd2->pPins->dDelayBlockMax : 0.0); }
float Mio_LibraryReadDelayAigNode ( Mio_Library_t * pLib ) { return pLib->pGateAnd2 ? Mio_LibraryReadDelayAnd2Max(pLib) : Mio_LibraryReadDelayNand2Max(pLib); } // approximate delay of the AIG node
float Mio_LibraryReadAreaInv ( Mio_Library_t * pLib ) { return (float)(pLib->pGateInv? pLib->pGateInv->dArea : 0.0); }
float Mio_LibraryReadAreaBuf ( Mio_Library_t * pLib ) { return (float)(pLib->pGateBuf? pLib->pGateBuf->dArea : 0.0); }
float Mio_LibraryReadAreaNand2 ( Mio_Library_t * pLib ) { return (float)(pLib->pGateNand2? pLib->pGateNand2->dArea : 0.0); }