Alan Mishchenko a78fb767ee Adding platform-independent (alphabetic) way of sorting Genlib gates and selecting representatives based on area/delay.

2015-04-17 21:02:15 +09:00

..

amap

Fixed a typo in variable names.

2015-02-07 22:29:14 -08:00

cov

Adding a wrapper around clock() for more accurate time counting in ABC.

2013-05-27 15:09:23 -07:00

fpga

Patching ABC for Yosys.

2013-11-27 12:17:00 -08:00

if

Support for representing programmable cell configuration data (bug fix).

2015-03-09 08:36:22 -07:00

mapper

Fixed a typo in variable names.

2015-02-07 22:29:14 -08:00

mio

Adding platform-independent (alphabetic) way of sorting Genlib gates and selecting representatives based on area/delay.

2015-04-17 21:02:15 +09:00

mpm

Improvements to representation of choices.

2014-07-01 13:05:09 -07:00

scl

Corner case bug in wire-cap estimation.

2015-02-18 09:18:01 -08:00

super

Fixed a typo in variable names.

2015-02-07 22:29:14 -08:00