Opensource DDR3 Controller

controller ddr3 ddr3-controller ddr3-phy fpga memory-controller phy verilog

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AngeloJacobo 20953ee65f fixed bug when ODELAY is not supported, clean file header and description		2023-11-09 13:25:39 +08:00
kintex_switch_files	add wbscope	2023-09-15 20:05:31 +08:00
rtl	fixed bug when ODELAY is not supported, clean file header and description	2023-11-09 13:25:39 +08:00
testbench	update simulation files	2023-09-15 20:04:55 +08:00
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README.md	Update README.md	2023-09-21 21:27:53 +08:00
ddr3.sby	not yet working when real parameter is used	2023-08-24 18:03:12 +08:00
ddr3_controller.sby	set depth to 7 (minimum)	2023-07-13 18:43:47 +08:00
ddr3_dimm_micron_sim_behav.wcfg	update wave files	2023-09-15 20:00:29 +08:00
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run_compile.sh	script for running verilator, yosys, iverilog, and then symbiyosys	2023-07-24 17:33:56 +08:00

README.md

DDR3_Controller (This repo will SOON be documented)

🚧 👷‍♂️ 👷‍♂️ UNDER CONSTRUCTION 👷‍♂️ 👷‍♂️ 🚧

Developer won't be available until end of October, but will be back by first week of November to continue this project. Planned improvements:

User documentation
More elaborated comments on the verilog file
AXI interface
Reduce logic resource (by optimizing logic and by making some parts removable)
Pass hardware test for Arty S7 FPGA board (this is currently passing on a Kintex S7 FPGA board but ironically not yet fully tested on an Arty S7 since it does not have ODELAY which makes it unable to do write calibration FOR NOW)
and a lot more....