c5d387fa24
added reset sequence and formal assertions
...
- completed (mostly) the reset sequence
- added formal assertions and cover statements for reset sequence logic
- moved all parameters to this file
- fixed port widths
- converted IO ports to ANSI
2023-03-09 18:06:53 +08:00
71df6f7515
moved all parameters to the main verilog file
2023-03-09 18:01:58 +08:00
86e01b060e
Update README.md
2023-03-02 20:32:12 +08:00
084a681644
include directory on iverilog command
2023-03-02 20:20:14 +08:00
3633613c47
Update ddr3_controller.v
2023-03-02 20:12:28 +08:00
6b9607563e
added sby file for formal verif
2023-03-02 20:11:10 +08:00
0f6f52390c
added shell script for compiling RTL
2023-03-02 20:07:08 +08:00
38109d8297
added initial RTLs
2023-03-02 20:04:37 +08:00
23d946c51c
Initial commit
2023-03-02 19:44:58 +08:00
Angelo Jacobo