added sby file for formal verif

2023-03-02 20:11:10 +08:00 · 2023-03-02 20:11:10 +08:00 · 6b9607563e
parent 0f6f52390c
commit 6b9607563e
1 changed files with 13 additions and 0 deletions
--- a/ddr3_controller.sby
+++ b/ddr3_controller.sby
@ -0,0 +1,13 @@
+[options]
+mode prove
+
+[engines]
+smtbmc
+
+[script]
+read -formal ddr3_controller.v
+prep -top ddr3_controller
+
+[files]
+./rtl/ddr3_controller.v
+./rtl/ddr3_parameters.vh