added shell script for compiling RTL

2023-03-02 20:07:08 +08:00 · 2023-03-02 20:07:08 +08:00 · 0f6f52390c
parent 38109d8297
commit 0f6f52390c
1 changed files with 15 additions and 0 deletions
--- a/run.sh
+++ b/run.sh
@ -0,0 +1,15 @@
+if [ "$1" == "" ]
+then
+    yosys -q -p "
+    read_verilog -sv ./rtl/ddr3_controller.v;
+    synth -top ddr3_controller"
+
+elif [ "$1" == "iverilog" ] 
+then
+    iverilog ./rtl/ddr3_controller.v -o .out
+    vvp .out
+
+fi
+
+# :set fileformat=unix
+