AngeloJacobo
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83b7b95af4
|
pass verilator warning
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2023-08-20 12:32:51 +08:00 |
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AngeloJacobo
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e2653d5793
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reset for IO is released only after IDELAYCTRL is ready, added also IODELAY_GROUP
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2023-08-20 11:09:38 +08:00 |
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AngeloJacobo
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9769a7cfaa
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pass formal for 8-lane config and pass verilator linting
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2023-08-20 11:07:22 +08:00 |
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AngeloJacobo
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36c93689e5
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redo read/write calibration if data read is wrong
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2023-08-17 11:27:23 +08:00 |
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AngeloJacobo
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f296d08c6b
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add option for ODELAY_SUPPORTED=0 and added port for i_ddr3_clk_90
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2023-08-15 19:37:28 +08:00 |
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AngeloJacobo
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411febc1a8
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add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY)
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2023-08-15 19:35:44 +08:00 |
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AngeloJacobo
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b3ab21a6d5
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add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY)
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2023-08-15 19:12:49 +08:00 |
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AngeloJacobo
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e9f1ab4971
|
modify debug port logic for wbscope
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2023-08-04 07:57:09 +08:00 |
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AngeloJacobo
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0753e6e157
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fixed localparam value for wb_addr_bits
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2023-08-04 07:53:12 +08:00 |
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AngeloJacobo
|
72dc00742b
|
correct generate indexes
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2023-08-04 07:52:31 +08:00 |
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AngeloJacobo
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1bfd851a6e
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pass formal with LANES either 1,2,4,8
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2023-08-04 07:49:25 +08:00 |
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AngeloJacobo
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2c73f38f99
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added debug port and max function for int type
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2023-08-01 15:58:58 +08:00 |
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AngeloJacobo
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d5f1d600ea
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resolve verilator warnings and add option YOSYS for not using input real in functions
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2023-07-24 17:27:17 +08:00 |
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AngeloJacobo
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60e40f9d35
|
less simulation warning
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2023-07-19 18:48:31 +08:00 |
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AngeloJacobo
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e38859ef78
|
resolved warning from vivado on IOBDELAY
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2023-07-19 18:47:24 +08:00 |
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AngeloJacobo
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7142dd9cdb
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added more registers and formal assertions to wb2
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2023-07-19 18:46:36 +08:00 |
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AngeloJacobo
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137e30ba36
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resolve vivado warnings
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2023-07-17 21:39:07 +08:00 |
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AngeloJacobo
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97e740139f
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resolved vivado warnings
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2023-07-17 21:38:20 +08:00 |
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AngeloJacobo
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983919d9df
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removed unneeded .* files
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2023-07-16 08:52:10 +08:00 |
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AngeloJacobo
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4f857e08f4
|
add files back after git rm -r cached .
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2023-07-16 08:46:16 +08:00 |
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AngeloJacobo
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b16c4d56cd
|
fixed error due to missing port dm and incorrect IO type for aux
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2023-07-16 08:39:24 +08:00 |
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AngeloJacobo
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b80bda4a46
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resolve warning from verilator linting
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2023-07-16 08:38:20 +08:00 |
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AngeloJacobo
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019722bc70
|
resolve warnings and errors from verilator linting
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2023-07-16 08:17:55 +08:00 |
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AngeloJacobo
|
ee83028986
|
make stall and accessible outside, removed added assumptions with i_slave_busy
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2023-07-13 18:48:34 +08:00 |
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AngeloJacobo
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2541d0afcc
|
added wishbone 2 ports
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2023-07-13 18:45:43 +08:00 |
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AngeloJacobo
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6fef8081ce
|
delete copy
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2023-07-13 18:45:00 +08:00 |
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AngeloJacobo
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47766cb8e8
|
added wishbone 2 and formally verified it
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2023-07-13 18:41:25 +08:00 |
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AngeloJacobo
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5904a4910d
|
shortened formal depth from 9 to 7
|
2023-07-09 09:34:03 +08:00 |
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AngeloJacobo
|
b03ca1864f
|
shortened formal depth from 17 to 9
|
2023-07-08 10:19:58 +08:00 |
|
AngeloJacobo
|
b3c9bdb650
|
pass test for timing params with depth of 9
|
2023-07-06 20:29:50 +08:00 |
|
AngeloJacobo
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10c290f9f8
|
temp newest version
|
2023-07-05 19:46:18 +08:00 |
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AngeloJacobo
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3250d8d368
|
write dqs toggles for half slow clk cycle at the end, needed when DQ is set to be delayed (non-zero flyby delay)
|
2023-07-05 16:41:55 +08:00 |
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AngeloJacobo
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ce3ca7e158
|
pre-refresh delay is now flexible and not fixed. Separated formal properties for testing time parameters
|
2023-07-05 16:35:57 +08:00 |
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AngeloJacobo
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217770b977
|
verified precharge and activate cmds, fixed bug in write_calib cmd
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2023-07-02 06:38:33 +08:00 |
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AngeloJacobo
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188b26ee12
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assume no request when slave busy (calibration or at refresh)
|
2023-06-29 12:58:41 +08:00 |
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AngeloJacobo
|
760c75d238
|
passes optimized pipeline stall control and passed fwb_slave properties
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2023-06-29 12:56:24 +08:00 |
|
AngeloJacobo
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2cfbba6d28
|
change ff to unix
|
2023-06-24 08:04:21 +08:00 |
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AngeloJacobo
|
2221a739db
|
add 2 clocks in prestall delay to pass tWR violation, add more asserts for fwb_slave
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2023-06-24 07:46:09 +08:00 |
|
AngeloJacobo
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b0e3b83e96
|
added wb properties from zipcpu repo
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2023-06-22 19:54:39 +08:00 |
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AngeloJacobo
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ef10bfd455
|
add data mask port
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2023-06-22 19:52:45 +08:00 |
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AngeloJacobo
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272711762e
|
add phy for data mask (oserdes -> odelay -> obuf)
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2023-06-22 19:51:06 +08:00 |
|
AngeloJacobo
|
0ffdacf6e7
|
add logic for write wb_ack, wb_sel, and aux
|
2023-06-22 19:49:05 +08:00 |
|
AngeloJacobo
|
0923fdc0b6
|
add formal assertions using fifo to prove every wb request has a corresponding read/write command output
|
2023-06-15 17:43:15 +08:00 |
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AngeloJacobo
|
053a511144
|
set write-to-read delay for all banks for every write
|
2023-06-10 08:19:16 +08:00 |
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AngeloJacobo
|
806b49ebd5
|
changed folder name with underscore
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2023-06-08 14:05:35 +08:00 |
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AngeloJacobo
|
f3e15e9ea4
|
added test 1: Sequential write then sequential read
|
2023-06-08 13:56:54 +08:00 |
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AngeloJacobo
|
2e6c2183aa
|
added sim duration for possible bus delays
|
2023-06-08 13:55:20 +08:00 |
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AngeloJacobo
|
de37c5a972
|
added wires for loadingg delay tap
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2023-06-08 13:53:07 +08:00 |
|
AngeloJacobo
|
b9204332b1
|
made delay tap loadable
|
2023-06-08 13:52:04 +08:00 |
|
AngeloJacobo
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c3707dab53
|
made delay tap loadable and made delay more flexible to use all 32 taps for both dqs and dq
|
2023-06-08 11:01:56 +08:00 |