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UberDDR3
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16 Commits

Author SHA1 Message Date
Angelo Jacobo 73e5f6b3de
added begin-end in short if-else statement 2023-03-23 20:35:37 +08:00
Angelo Jacobo 2018aa7ef7
changed license to Apache 2.0 2023-03-23 20:18:46 +08:00
Angelo Jacobo 97092cf869
added logic for refresh sequence and bank access 2023-03-23 20:17:12 +08:00
Angelo Jacobo 59ac654990
Delete LICENSE 2023-03-23 20:10:22 +08:00
Angelo Jacobo 973e0a5df1
Update README.md 2023-03-13 14:40:46 +08:00
Angelo Jacobo 7282e2565d
removed parameter file "ddr3_parameters.vh" 2023-03-09 18:16:01 +08:00
Angelo Jacobo adb21070d4
used :retab and fixed tab spacing 2023-03-09 18:14:58 +08:00
Angelo Jacobo c5d387fa24
added reset sequence and formal assertions 
- completed (mostly) the reset sequence
- added formal assertions and cover statements for reset sequence logic
- moved all parameters to this file
- fixed port widths
- converted IO ports to ANSI
 2023-03-09 18:06:53 +08:00
Angelo Jacobo 71df6f7515
moved all parameters to the main verilog file 2023-03-09 18:01:58 +08:00
Angelo Jacobo 86e01b060e
Update README.md 2023-03-02 20:32:12 +08:00
Angelo Jacobo 084a681644
include directory on iverilog command 2023-03-02 20:20:14 +08:00
Angelo Jacobo 3633613c47
Update ddr3_controller.v 2023-03-02 20:12:28 +08:00
Angelo Jacobo 6b9607563e
added sby file for formal verif 2023-03-02 20:11:10 +08:00
Angelo Jacobo 0f6f52390c
added shell script for compiling RTL 2023-03-02 20:07:08 +08:00
Angelo Jacobo 38109d8297
added initial RTLs 2023-03-02 20:04:37 +08:00
Angelo Jacobo 23d946c51c
Initial commit 2023-03-02 19:44:58 +08:00