Angelo Jacobo
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71df6f7515
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moved all parameters to the main verilog file
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2023-03-09 18:01:58 +08:00 |
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Angelo Jacobo
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86e01b060e
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Update README.md
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2023-03-02 20:32:12 +08:00 |
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Angelo Jacobo
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084a681644
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include directory on iverilog command
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2023-03-02 20:20:14 +08:00 |
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Angelo Jacobo
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3633613c47
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Update ddr3_controller.v
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2023-03-02 20:12:28 +08:00 |
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Angelo Jacobo
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6b9607563e
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added sby file for formal verif
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2023-03-02 20:11:10 +08:00 |
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Angelo Jacobo
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0f6f52390c
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added shell script for compiling RTL
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2023-03-02 20:07:08 +08:00 |
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Angelo Jacobo
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38109d8297
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added initial RTLs
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2023-03-02 20:04:37 +08:00 |
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Angelo Jacobo
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23d946c51c
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Initial commit
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2023-03-02 19:44:58 +08:00 |