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d0526b524bec5b143b69990ed9512869629c7eac
OpenSTA/test
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Akash LevyandCursor d0526b524b FEATURE: Implement set_max_dynamic_power and set_max_leakage_power (#471) 
* Implement set_max_dynamic_power and set_max_leakage_power.

Store max dynamic/leakage power like max area, expose getters through Sta,
write them in write_sdc, and document that they are ignored during timing.

Co-authored-by: Cursor <[email protected]>

* Drop get_max_* Tcl wrappers; use SWIG accessors in tests.

James pointed out the get_max_* commands duplicate existing SWIG
accessors; remove them and call sta::max_* from the regression.

Co-authored-by: Cursor <[email protected]>

---------

Co-authored-by: Cursor <[email protected]>
2026-07-31 12:57:23 -07:00
..
asap7_ccsn.lib.gz
CCSN PR fixes (#178)
2025-01-16 09:35:38 -08:00
asap7_invbuf.lib.gz
CCS sim delay calc
2024-04-19 17:27:21 -07:00
asap7_seq.lib.gz
prima delay calc
2024-06-30 14:44:31 -07:00
asap7_simple.lib.gz
prima delay calc
2024-06-30 14:44:31 -07:00
asap7_small.lib.gz
asap7_small cmmment
2026-07-09 10:34:44 -07:00
delay_calc.ok
regression update
2022-12-31 16:36:24 -07:00
disconnect_mcp_pin.ok
rel 3.0
2026-01-13 09:36:45 -07:00
disconnect_mcp_pin.tcl
disconnect/disconnect pin set_multicycle_path resolves #327
2025-11-13 10:06:57 -07:00
disconnect_mcp_pin.v
disconnect/disconnect pin set_multicycle_path resolves #327
2025-11-13 10:06:57 -07:00
get_filter.ok
get_* -filter allow true/false, '.' in glob pattern resolves #416
2026-04-04 16:19:41 -07:00
get_filter.tcl
rm unnecessary sta:: in tcl
2026-04-16 16:12:59 -07:00
get_is_buffer.ok
Fix isBuffer (#329)
2025-11-16 15:34:37 -08:00
get_is_buffer.tcl
Fix isBuffer (#329)
2025-11-16 15:34:37 -08:00
get_is_buffer.v
Fix isBuffer (#329)
2025-11-16 15:34:37 -08:00
get_is_memory.ok
Make is_memory property more sensitive for cells and libcells by also matching on memory groups (#129)
2024-11-20 15:10:12 -08:00
get_is_memory.tcl
liberty reader rewrite
2026-02-27 17:12:50 -08:00
get_is_memory.v
Make is_memory property more sensitive for cells and libcells by also matching on memory groups (#129)
2024-11-20 15:10:12 -08:00
get_lib_pins_of_objects.ok
get_* -filter allow true/false, '.' in glob pattern resolves #416
2026-04-04 16:19:41 -07:00
get_lib_pins_of_objects.tcl
Add -of_objects key to get_lib_pins (#128)
2024-11-16 14:05:34 -08:00
get_noargs.ok
get_* -filter allow true/false, '.' in glob pattern resolves #416
2026-04-04 16:19:41 -07:00
get_noargs.tcl
Revisions
2024-09-24 21:20:10 -07:00
get_objrefs.ok
get_* -filter allow true/false, '.' in glob pattern resolves #416
2026-04-04 16:19:41 -07:00
get_objrefs.tcl
Revisions
2024-09-24 21:20:10 -07:00
get_scenes.ok
Add property-based -filter to get_scenes / get_modes, and make Scene/Mode properties extensible (#456)
2026-07-10 09:37:48 -07:00
get_scenes.tcl
Add property-based -filter to get_scenes / get_modes, and make Scene/Mode properties extensible (#456)
2026-07-10 09:37:48 -07:00
gf180mcu_sram.lib.gz
liberty reader rewrite
2026-02-27 17:12:50 -08:00
helpers.tcl
test/helpers.tcl
2026-02-26 09:32:20 -08:00
input_delay_ref_pin_rebuild.ok
fix missing path issue (#452)
2026-06-25 16:55:29 -07:00
input_delay_ref_pin_rebuild.tcl
fix missing path issue (#452)
2026-06-25 16:55:29 -07:00
liberty_arcs_one2one_1.lib
Follow testing guidelines and specify unateness
2024-09-13 00:57:41 -07:00
liberty_arcs_one2one_1.ok
liberty reader rewrite
2026-02-27 17:12:50 -08:00
liberty_arcs_one2one_1.tcl
Follow testing guidelines and specify unateness
2024-09-13 00:57:41 -07:00
liberty_arcs_one2one_1.v
Rename files as requested
2024-08-01 21:14:48 -07:00
liberty_arcs_one2one_2.lib
Follow testing guidelines and specify unateness
2024-09-13 00:57:41 -07:00
liberty_arcs_one2one_2.ok
liberty reader rewrite
2026-02-27 17:12:50 -08:00
liberty_arcs_one2one_2.tcl
Follow testing guidelines and specify unateness
2024-09-13 00:57:41 -07:00
liberty_arcs_one2one_2.v
Rename files as requested
2024-08-01 21:14:48 -07:00
liberty_backslash_eol.lib
Allow backslash-EOL to end tokens in Liberty file (#279)
2025-07-31 12:19:36 -07:00
liberty_backslash_eol.ok
Allow backslash-EOL to end tokens in Liberty file (#279)
2025-07-31 12:19:36 -07:00
liberty_backslash_eol.tcl
Allow backslash-EOL to end tokens in Liberty file (#279)
2025-07-31 12:19:36 -07:00
liberty_ccsn.ok
Ignore CCSN groups (#176)
2025-01-15 09:35:40 -08:00
liberty_ccsn.tcl
CCSN PR fixes (#178)
2025-01-16 09:35:38 -08:00
liberty_float_as_str.lib
Allow Liberty floats as strings for voltage_map and capacitive_load_unit (#280)
2025-08-01 17:41:56 -07:00
liberty_float_as_str.ok
Allow Liberty floats as strings for voltage_map and capacitive_load_unit (#280)
2025-08-01 17:41:56 -07:00
liberty_float_as_str.tcl
Allow Liberty floats as strings for voltage_map and capacitive_load_unit (#280)
2025-08-01 17:41:56 -07:00
liberty_latch3.lib
Fix for non-standard latches (#151)
2024-12-19 15:02:03 -08:00
liberty_latch3.ok
Fix for non-standard latches (#151)
2024-12-19 15:02:03 -08:00
liberty_latch3.tcl
Fix for non-standard latches (#151)
2024-12-19 15:02:03 -08:00
make_concrete_parasitics_leak.ok
fix makeConcreteParasitics leak+testcase (#439)
2026-05-20 13:55:02 -07:00
make_concrete_parasitics_leak.tcl
fix makeConcreteParasitics leak+testcase (#439)
2026-05-20 13:55:02 -07:00
max_power_area.ok
FEATURE: Implement set_max_dynamic_power and set_max_leakage_power (#471)
2026-07-31 12:57:23 -07:00
max_power_area.tcl
FEATURE: Implement set_max_dynamic_power and set_max_leakage_power (#471)
2026-07-31 12:57:23 -07:00
mcmm3.ok
rel 3.0
2026-01-13 09:36:45 -07:00
min_max_delays.ok
regression update
2022-12-31 16:36:24 -07:00
multi_corner.ok
regression update
2022-12-31 16:36:24 -07:00
package_require.ok
Package require test (#303)
2025-10-04 10:36:22 -07:00
package_require.tcl
Package require test (#303)
2025-10-04 10:36:22 -07:00
path_group_names.ok
Sta::isPathGroupName
2025-10-26 09:23:16 -07:00
path_group_names.tcl
All path groups (#215)
2025-02-12 10:40:43 -08:00
power_json.ok
fix and simplify power_json test
2025-12-20 10:45:17 -07:00
power_json.tcl
rel 3.0
2026-01-13 09:36:45 -07:00
power_vcd.ok
rel 3.0
2026-01-13 09:36:45 -07:00
power.ok
rel 3.0
2026-01-13 09:36:45 -07:00
prima3.ok
report_dcalc prima resolves #418
2026-04-07 10:45:04 -07:00
prima3.tcl
report_dcalc prima resolves #418
2026-04-07 10:45:04 -07:00
prima_singular.ok
PrimaDelayCalc: handle degenerate parasitic networks (fixes STA-1752 "G matrix is singular") (#476)
2026-07-27 08:48:57 -07:00
prima_singular.spef
PrimaDelayCalc: handle degenerate parasitic networks (fixes STA-1752 "G matrix is singular") (#476)
2026-07-27 08:48:57 -07:00
prima_singular.tcl
PrimaDelayCalc: handle degenerate parasitic networks (fixes STA-1752 "G matrix is singular") (#476)
2026-07-27 08:48:57 -07:00
prima_singular.v
PrimaDelayCalc: handle degenerate parasitic networks (fixes STA-1752 "G matrix is singular") (#476)
2026-07-27 08:48:57 -07:00
read_saif_null_instance.lib
read_saif ref missing instance resolves #406
2026-03-24 10:31:24 -07:00
read_saif_null_instance.ok
read_saif ref missing instance resolves #406
2026-03-24 10:31:24 -07:00
read_saif_null_instance.saif
read_saif ref missing instance resolves #406
2026-03-24 10:31:24 -07:00
read_saif_null_instance.tcl
read_saif ref missing instance resolves #406
2026-03-24 10:31:24 -07:00
read_saif_null_instance.v
read_saif ref missing instance resolves #406
2026-03-24 10:31:24 -07:00
reg1_asap7.spef
prima delay calc
2024-06-30 14:44:31 -07:00
reg1_asap7.v
prima delay calc
2024-06-30 14:44:31 -07:00
regression
regression sta_dir
2026-02-27 17:54:32 -08:00
regression_vars.tcl
FEATURE: Implement set_max_dynamic_power and set_max_leakage_power (#471)
2026-07-31 12:57:23 -07:00
regression.tcl
regression
2026-05-06 08:51:10 -07:00
report_checks_sorted.ok
search: fix truncating path ends list if sorting by slack (#291)
2025-09-03 16:45:33 -07:00
report_checks_sorted.tcl
search: fix truncating path ends list if sorting by slack (#291)
2025-09-03 16:45:33 -07:00
report_checks_sorted.v
search: fix truncating path ends list if sorting by slack (#291)
2025-09-03 16:45:33 -07:00
report_checks_src_attr.ok
Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)
2025-01-13 19:28:04 -08:00
report_checks_src_attr.tcl
Add src_attr field (#108)
2024-10-15 17:28:52 -07:00
report_json1.ok
Add GitHub Action for CI and fix broken testcases (#391)
2026-02-27 13:51:28 -08:00
report_json1.tcl
report_json1/2.tcl rm redirection
2025-01-15 09:24:53 -07:00
report_json2.ok
Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)
2025-01-13 19:28:04 -08:00
report_json2.tcl
report_json1/2.tcl rm redirection
2025-01-15 09:24:53 -07:00
save_ok
fix and simplify power_json test
2025-12-20 10:45:17 -07:00
sdf_delays.ok
regression update
2022-12-31 16:36:24 -07:00
spef_parasitics.ok
regression update
2022-12-31 16:36:24 -07:00
suppress_msg.ok
Add GitHub Action for CI and fix broken testcases (#391)
2026-02-27 13:51:28 -08:00
suppress_msg.tcl
Add error/warning suppression with suppress_msg and unsuppress_msg commands (#157)
2025-01-17 11:20:19 -08:00
user_properties.ok
Extend user-defined properties to all basic object types (#479)
2026-07-27 08:50:40 -07:00
user_properties.tcl
Extend user-defined properties to all basic object types (#479)
2026-07-27 08:50:40 -07:00
valgrind.suppress
regression fast
2019-08-09 18:44:31 -07:00
vcd_begin_end_time.ok
FEATURE: Add read_vcd -begin_time/-end_time activity windowing (#466)
2026-07-29 08:44:51 -07:00
vcd_begin_end_time.tcl
FEATURE: Add read_vcd -begin_time/-end_time activity windowing (#466)
2026-07-29 08:44:51 -07:00
vcd_begin_end_time.v
FEATURE: Add read_vcd -begin_time/-end_time activity windowing (#466)
2026-07-29 08:44:51 -07:00
vcd_begin_end_time.vcd
FEATURE: Add read_vcd -begin_time/-end_time activity windowing (#466)
2026-07-29 08:44:51 -07:00
verilog_attribute.ok
Fix parsing error with >2 attributes
2024-03-27 19:33:58 -07:00
verilog_attribute.tcl
verilog c++ parser
2025-01-21 18:35:21 -07:00
verilog_attribute.v
Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)
2025-01-13 19:28:04 -08:00
verilog_specify.ok
Recognize some basic specify blocks and ignore them (#309)
2025-10-12 14:11:00 -07:00
verilog_specify.tcl
Recognize some basic specify blocks and ignore them (#309)
2025-10-12 14:11:00 -07:00
verilog_specify.v
Recognize some basic specify blocks and ignore them (#309)
2025-10-12 14:11:00 -07:00
verilog_unconnected_hpin.ok
Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression (#401)
2026-03-10 14:57:21 -07:00
verilog_unconnected_hpin.tcl
Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression (#401)
2026-03-10 14:57:21 -07:00
verilog_unconnected_hpin.v
Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression (#401)
2026-03-10 14:57:21 -07:00
verilog_well_supplies.ok
Bias pin handling (#409)
2026-04-07 11:00:01 -07:00
verilog_well_supplies.tcl
Bias pin handling (#409)
2026-04-07 11:00:01 -07:00
verilog_well_supplies.v
Bias pin handling (#409)
2026-04-07 11:00:01 -07:00
verilog_write_escape.ok
Write verilog escape (#394)
2026-03-02 16:48:15 -08:00
verilog_write_escape.tcl
Write verilog escape (#394)
2026-03-02 16:48:15 -08:00
verilog_write_escape.v
Write verilog escape (#394)
2026-03-02 16:48:15 -08:00
verilog_write_gzip.ok
Add native gzip compression support to write_verilog (#448)
2026-06-10 09:12:19 -07:00
verilog_write_gzip.tcl
Add native gzip compression support to write_verilog (#448)
2026-06-10 09:12:19 -07:00
write_path_spice_arc_sense.cells.spice
write_path_spice: match side input values to the path arc's transitions (#475)
2026-07-27 10:23:15 -07:00
write_path_spice_arc_sense.lib.gz
write_path_spice: match side input values to the path arc's transitions (#475)
2026-07-27 10:23:15 -07:00
write_path_spice_arc_sense.models.spice
write_path_spice: match side input values to the path arc's transitions (#475)
2026-07-27 10:23:15 -07:00
write_path_spice_arc_sense.ok
write_path_spice: match side input values to the path arc's transitions (#475)
2026-07-27 10:23:15 -07:00
write_path_spice_arc_sense.tcl
write_path_spice: match side input values to the path arc's transitions (#475)
2026-07-27 10:23:15 -07:00
write_path_spice_arc_sense.v
write_path_spice: match side input values to the path arc's transitions (#475)
2026-07-27 10:23:15 -07:00