PrimaDelayCalc: handle degenerate parasitic networks (fixes STA-1752 "G matrix is singular") (#476)
* support for filter in get_scene/mode Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * fix singular G matrix issue for degenerate nets Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * fix the mistake on existing regression- was accidentally modified Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * make changes accounting for future SI support and address reviews Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * simplify comment Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * address feedbacks Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> --------- Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
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Deepashree Sengupta
GitHub
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@ -467,35 +467,79 @@ PrimaDelayCalc::findNodeCount()
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pin_node_map_.clear();
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node_index_map_.clear();
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for (ParasiticNode *node : parasitics_->nodes(parasitic_network_)) {
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if (!parasitics_->isExternal(node)) {
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size_t node_idx = node_index_map_.size();
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node_index_map_[node] = node_idx;
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const Pin *pin = parasitics_->pin(node);
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if (pin) {
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pin_node_map_[pin] = node_idx;
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debugPrint(debug_, "ccs_dcalc", 1, "pin {} node {}",
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network_->pathName(pin), node_idx);
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// Collect the nodes that enter G by walking out from the drivers through
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// resistors. G is conductance-only, so a node with no resistive path to a
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// driver has an all-zero row which is dropped to prevent singularity.
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ParasiticNodeResistorMap resistor_map =
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parasitics_->parasiticNodeResistorMap(parasitic_network_);
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std::vector<ParasiticNode *> queue;
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for (size_t drvr_idx = 0; drvr_idx < drvr_count_; drvr_idx++) {
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const Pin *drvr_pin = (*dcalc_args_)[drvr_idx].drvrPin();
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ParasiticNode *drvr_node =
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parasitics_->findParasiticNode(parasitic_network_, drvr_pin);
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if (drvr_node && !parasitics_->isExternal(drvr_node)
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&& !node_index_map_.contains(drvr_node))
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placeNode(drvr_node, node_capacitances_.size(), queue);
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}
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while (!queue.empty()) {
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ParasiticNode *node = queue.back();
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queue.pop_back();
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size_t node_index = node_index_map_[node];
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auto resistor_itr = resistor_map.find(node);
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if (resistor_itr != resistor_map.end()) {
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for (ParasiticResistor *resistor : resistor_itr->second) {
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ParasiticNode *next_node = parasitics_->otherNode(resistor, node);
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if (next_node
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&& !parasitics_->isExternal(next_node)
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&& !node_index_map_.contains(next_node)) {
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bool shorted = parasitics_->value(resistor) <= 0.0;
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placeNode(next_node, shorted ? node_index : node_capacitances_.size(),
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queue);
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}
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}
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double cap = parasitics_->nodeGndCap(node) + pinCapacitance(node);
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node_capacitances_.push_back(cap);
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}
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}
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// Lump each coupling capacitor to ground at its internal (non-external)
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// nodes that made it into the network.
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for (ParasiticCapacitor *capacitor : parasitics_->capacitors(parasitic_network_)) {
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float cap = parasitics_->value(capacitor) * coupling_cap_multiplier_;
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ParasiticNode *node1 = parasitics_->node1(capacitor);
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if (node1 && !parasitics_->isExternal(node1)) {
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size_t node_idx = node_index_map_[node1];
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node_capacitances_[node_idx] += cap;
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auto itr = node_index_map_.find(node1);
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if (itr != node_index_map_.end())
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node_capacitances_[itr->second] += cap;
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}
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ParasiticNode *node2 = parasitics_->node2(capacitor);
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if (node2 && !parasitics_->isExternal(node2)) {
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size_t node_idx = node_index_map_[node2];
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node_capacitances_[node_idx] += cap;
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auto itr = node_index_map_.find(node2);
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if (itr != node_index_map_.end())
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node_capacitances_[itr->second] += cap;
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}
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}
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node_count_ = node_index_map_.size();
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node_count_ = node_capacitances_.size();
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}
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// Add node to the conductance system at index (shared by drivers and by the
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// resistor walk); a merged short reuses its near node's index. Accumulates the
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// node's ground capacitance and queues it for the walk.
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void
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PrimaDelayCalc::placeNode(ParasiticNode *node,
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size_t index,
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std::vector<ParasiticNode*> &queue)
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{
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node_index_map_[node] = index;
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if (index == node_capacitances_.size())
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node_capacitances_.push_back(0.0);
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node_capacitances_[index] +=
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parasitics_->nodeGndCap(node) + pinCapacitance(node);
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const Pin *pin = parasitics_->pin(node);
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if (pin) {
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pin_node_map_[pin] = index;
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debugPrint(debug_, "ccs_dcalc", 1, "pin {} node {}",
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network_->pathName(pin), index);
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}
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queue.push_back(node);
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}
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float
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@ -568,13 +612,17 @@ PrimaDelayCalc::stampEqns()
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resistance_sum_ = 0.0;
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for (ParasiticResistor *resistor : parasitics_->resistors(parasitic_network_)) {
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ParasiticNode *node1 = parasitics_->node1(resistor);
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ParasiticNode *node2 = parasitics_->node2(resistor);
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// One commercial extractor creates resistors with identical from/to nodes.
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if (node1 != node2) {
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size_t node_idx1 = node_index_map_[node1];
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size_t node_idx2 = node_index_map_[node2];
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float resistance = parasitics_->value(resistor);
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auto itr1 = node_index_map_.find(parasitics_->node1(resistor));
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auto itr2 = node_index_map_.find(parasitics_->node2(resistor));
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// Skip a resistor with a node left out of the network.
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if (itr1 == node_index_map_.end() || itr2 == node_index_map_.end())
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continue;
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size_t node_idx1 = itr1->second;
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size_t node_idx2 = itr2->second;
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float resistance = parasitics_->value(resistor);
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// Skip a self loop / merged short (same index) or a non-positive (short)
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// resistance; stamping 1/resistance would be infinite.
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if (node_idx1 != node_idx2 && resistance > 0.0) {
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stampConductance(node_idx1, node_idx2, 1.0 / resistance);
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resistance_sum_ += resistance;
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}
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@ -132,6 +132,9 @@ protected:
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void initSim();
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void findLoads();
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void findNodeCount();
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void placeNode(ParasiticNode *node,
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size_t index,
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std::vector<ParasiticNode*> &queue);
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void setOrder();
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void initCeffIdrvr();
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void setXinit();
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@ -0,0 +1,28 @@
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Startpoint: r0 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: t0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (propagated)
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0.00 0.00 ^ r0/CLK (DFFHQx4_ASAP7_75t_R)
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68.24 68.24 ^ r0/Q (DFFHQx4_ASAP7_75t_R)
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52.16 120.40 ^ u0/Y (BUFx2_ASAP7_75t_R)
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18.40 138.80 ^ t0/D (DFFHQx4_ASAP7_75t_R)
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138.80 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (propagated)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ t0/CLK (DFFHQx4_ASAP7_75t_R)
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-22.18 477.82 library setup time
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477.82 data required time
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---------------------------------------------------------
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477.82 data required time
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-138.80 data arrival time
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---------------------------------------------------------
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339.02 slack (MET)
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@ -0,0 +1,52 @@
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*SPEF "IEEE 1481-1998"
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*DESIGN "top"
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*DATE "2026"
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*VENDOR "OpenSTA test"
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*PROGRAM "hand written"
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*VERSION "1.0.1c"
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*DESIGN_FLOW "MISSING_NETS"
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*DIVIDER /
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*DELIMITER :
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*BUS_DELIMITER [ ]
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*T_UNIT 1.0 PS
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*C_UNIT 1.0 FF
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*R_UNIT 1.0 KOHM
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*L_UNIT 1.0 UH
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// Each buffer output net z<i> is degenerate two ways:
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// - z<i>:2 z<i>:3 have ground cap but NO resistor (floating islands)
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// - u<i>:Y -- z<i>:1 is a 0 KOHM resistor (an ideal short)
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// Both used to make PrimaDelayCalc::primaReduce() factorize a singular G
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// (STA-1752). node_count_ = 5 > prima_order_ (default 3) selects the
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// primaReduce() path that factorizes the pure G matrix.
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*D_NET z0 40.2
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*CONN
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*I u0:Y O
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*I t0:D I *L .0086
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*CAP
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1 u0:Y 6.7
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2 t0:D 6.7
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3 z0:1 6.7
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4 z0:2 6.7
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5 z0:3 6.7
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*RES
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6 u0:Y z0:1 0
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7 z0:1 t0:D 2.42
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*END
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*D_NET z1 40.2
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*CONN
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*I u1:Y O
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*I t1:D I *L .0086
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*CAP
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1 u1:Y 6.7
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2 t1:D 6.7
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3 z1:1 6.7
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4 z1:2 6.7
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5 z1:3 6.7
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*RES
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6 u1:Y z1:1 0
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7 z1:1 t1:D 2.42
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*END
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@ -0,0 +1,29 @@
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# Prima delay calc on degenerate parasitic networks (STA-1752 regression).
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#
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# Each buffer output net has both a floating (resistor-less) node and a
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# zero-resistance short. Either one used to make PrimaDelayCalc's conductance
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# matrix G singular, raising STA-1752 "G matrix is singular". Single threaded
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# this surfaced as a Tcl error; multi threaded the error was thrown from a
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# DispatchQueue worker and aborted with SIGABRT. findNodeCount() now drops
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# isolated nodes and merges shorted nodes, so the delay is computed correctly.
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#
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# This test runs single threaded and checks the reported path. To exercise the
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# historical multi-threaded crash path set STA_TEST_THREADS to the number of
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# parallel buffers (2); the run must still complete without aborting. (A BFS
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# level is dispatched to workers only when its vertex count >= the thread count,
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# so more threads than buffers runs inline on the main thread.)
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read_liberty asap7_small.lib.gz
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read_verilog prima_singular.v
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link_design top
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create_clock -name clk -period 500 clk
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set_input_delay -clock clk 1 [list in0 in1]
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set_input_transition 10 [list clk in0 in1]
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set_propagated_clock clk
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read_spef prima_singular.spef
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sta::set_delay_calculator prima
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if { [info exists ::env(STA_TEST_THREADS)] } {
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sta::set_thread_count $::env(STA_TEST_THREADS)
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} else {
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sta::set_thread_count 1
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}
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report_checks -group_path_count 1
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@ -0,0 +1,11 @@
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module top (clk, in0, in1, out0, out1);
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input clk, in0, in1;
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output out0, out1;
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wire q0, q1, z0, z1;
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DFFHQx4_ASAP7_75t_R r0 (.D(in0), .CLK(clk), .Q(q0));
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BUFx2_ASAP7_75t_R u0 (.A(q0), .Y(z0));
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DFFHQx4_ASAP7_75t_R t0 (.D(z0), .CLK(clk), .Q(out0));
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DFFHQx4_ASAP7_75t_R r1 (.D(in1), .CLK(clk), .Q(q1));
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BUFx2_ASAP7_75t_R u1 (.A(q1), .Y(z1));
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DFFHQx4_ASAP7_75t_R t1 (.D(z1), .CLK(clk), .Q(out1));
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endmodule
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@ -161,6 +161,7 @@ record_public_tests {
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path_group_names
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power_json
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prima3
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prima_singular
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read_saif_null_instance
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report_checks_sorted
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report_checks_src_attr
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