Rename files as requested

test/liberty_arcs_one2one.lib

@@ -1,4 +1,4 @@
-library (one_to_one_mismatched_width_test) {
+library (one_to_one_mismatched_width) {
   delay_model : "table_lookup";
   simulation : false;
   capacitive_load_unit (1,pF);

test/liberty_arcs_one2one.ok

@@ -1,5 +1,5 @@
-Warning: one2one.lib line 48, timing port A and related port Y are different sizes.
-Warning: one2one.lib line 76, timing port A and related port Y are different sizes.
+Warning: liberty_arcs_one2one.lib line 48, timing port A and related port Y are different sizes.
+Warning: liberty_arcs_one2one.lib line 76, timing port A and related port Y are different sizes.
 TEST 1:
 Startpoint: a[0] (input port clocked by clk)
 Endpoint: y[0] (output port clocked by clk)

test/liberty_arcs_one2one.tcl

@@ -1,16 +1,16 @@
-read_liberty one2one.lib
+read_liberty liberty_arcs_one2one.lib
 
 puts "TEST 1:"
-read_verilog one2one_test1.v
-link_design one2one_test1
+read_verilog liberty_arcs_one2one_1.v
+link_design liberty_arcs_one2one_1
 create_clock -name clk -period 0
 set_input_delay -clock clk 0 [all_inputs]
 set_output_delay -clock clk 0 [all_outputs]
 report_checks -group_count 5
 
 puts "TEST 2:"
-read_verilog one2one_test2.v
-link_design one2one_test2
+read_verilog liberty_arcs_one2one_2.v
+link_design liberty_arcs_one2one_2
 create_clock -name clk -period 0
 set_input_delay -clock clk 0 [all_inputs]
 set_output_delay -clock clk 0 [all_outputs]

test/liberty_arcs_one2one_1.v

@@ -1,6 +1,6 @@
 // Liberty file test: one-to-one mapping with mismatched bit widths
 // Should generate warning but still create timing arcs between bits with same index
-module one2one_test1 (
+module liberty_arcs_one2one_1 (
   input wire [7:0] a,
   output wire [3:0] y
 );

test/liberty_arcs_one2one_2.v

@@ -1,6 +1,6 @@
 // Liberty file test: one-to-one mapping with mismatched bit widths
 // Should generate warning but still create timing arcs between bits with same index
-module one2one_test2 (
+module liberty_arcs_one2one_2 (
   input wire [3:0] a,
   output wire [7:0] y
 );

test/regression_vars.tcl

@@ -124,7 +124,7 @@ record_example_tests {
 record_sta_tests {
   prima3
   verilog_attribute
-  one2one
+  liberty_arcs_one2one
 }
 
 define_test_group fast [group_tests all]