verilog c++ parser
commit 6fac3fee87a3309132b5bdbb731292ecd6410a86
Author: James Cherry <cherry@parallaxsw.com>
Date: Tue Jan 21 18:24:18 2025 -0700
Sta use VerilogReader class
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 05d4bce4bcfcfaa07392b237a596a82315b895b3
Author: James Cherry <cherry@parallaxsw.com>
Date: Tue Jan 21 15:14:29 2025 -0700
vparse
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit e977e89b62191688db5c815131fc389d9ce401c5
Author: James Cherry <cherry@parallaxsw.com>
Date: Tue Jan 21 11:30:46 2025 -0700
write_verilog missing port ddcl
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 1742d5d92533559235ea4c42d9ea4bf2d47fb943
Author: James Cherry <cherry@parallaxsw.com>
Date: Tue Jan 21 11:23:48 2025 -0700
verilog escape constexpr
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 226a23092312a37503100d49ab74d4fb1e5856ef
Author: James Cherry <cherry@parallaxsw.com>
Date: Mon Jan 20 09:34:32 2025 -0700
comment
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 63ca4ac5855710427e1ddfc5c2cba8998452d1f0
Author: James Cherry <cherry@parallaxsw.com>
Date: Sun Jan 19 19:45:48 2025 -0700
leaks
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit c1d38aa0cc983204b1bb3f49944709e74c831be7
Author: James Cherry <cherry@parallaxsw.com>
Date: Sun Jan 19 13:26:07 2025 -0700
verilog std::string
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 22607b41b9eb9fc71d53214893150afb757a8a56
Author: James Cherry <cherry@parallaxsw.com>
Date: Sun Jan 19 11:36:23 2025 -0700
verilog std::string
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit dba2bc939fc58d465229cc2d474705151cd50d05
Author: James Cherry <cherry@parallaxsw.com>
Date: Sun Jan 19 10:01:14 2025 -0700
verilog std::string
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 7d449041a2b75b874038af377d46130b45195a00
Author: James Cherry <cherry@parallaxsw.com>
Date: Sun Jan 19 09:18:55 2025 -0700
verilog std::string
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit d02495222838f037f25d131ce1b270a6121cf16f
Author: James Cherry <cherry@parallaxsw.com>
Date: Sun Jan 19 08:53:47 2025 -0700
verilog std::string
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 10c5c1040f26c8ebe295d245a641fc913e0ec9f5
Author: James Cherry <cherry@parallaxsw.com>
Date: Sat Jan 18 21:50:12 2025 -0700
verlog constant use std::string
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 21943c1b63fd36d12de1e5986905e14fe73ce7be
Author: James Cherry <cherry@parallaxsw.com>
Date: Sat Jan 18 17:41:43 2025 -0700
verilog std::string
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit c0232b71ea5137b37d055d83f3da194341aed7a0
Author: James Cherry <cherry@parallaxsw.com>
Date: Sat Jan 18 17:12:47 2025 -0700
verilog std::string
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit c68fd0329ee35b4877763bcdc82e8fe03a3b16de
Author: James Cherry <cherry@parallaxsw.com>
Date: Sat Jan 18 16:54:10 2025 -0700
verilog std::string
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 3e2dca2140db42acce390ec1a18f29ee4de3c631
Author: James Cherry <cherry@parallaxsw.com>
Date: Sat Jan 18 16:07:19 2025 -0700
vparse const
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 210196f9e5a63dfdd5ed45a418388b7ec74ade07
Author: James Cherry <cherry@parallaxsw.com>
Date: Sat Jan 18 12:31:13 2025 -0700
verilog parse centos7
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit b8e1882121ac1763e767d299fd929bdfb07c5ffb
Author: James Cherry <cherry@parallaxsw.com>
Date: Sat Jan 18 10:21:48 2025 -0700
verilog names string*
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit c455723c5801d2d7386e7d1d53a0f9fb501c0c03
Author: James Cherry <cherry@parallaxsw.com>
Date: Sat Jan 18 09:51:47 2025 -0700
verilog reader names
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 47307b1d8a61abab91195969be8708a7646bbfe3
Author: James Cherry <cherry@parallaxsw.com>
Date: Sat Jan 18 09:21:30 2025 -0700
valgrind
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 0de49ba76cb0d1e06f93868676b73b4cd2ee609e
Author: James Cherry <cherry@parallaxsw.com>
Date: Wed Jan 15 16:50:56 2025 -0700
suppress yynerrs_ warning
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit dbe2ba18d99d850ba5ebb1c75a4165bfff2df96d
Author: James Cherry <cherry@parallaxsw.com>
Date: Wed Jan 15 16:37:14 2025 -0700
cmake bison target names
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 388be6c2aa69b839a53be78bafab420216554944
Author: James Cherry <cherry@parallaxsw.com>
Date: Tue Jan 14 08:57:02 2025 -0700
network link func rm repor, network args
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit f50d5b23aff126e7d396a555f06eae5597ec1354
Author: James Cherry <cherry@parallaxsw.com>
Date: Mon Jan 13 19:48:44 2025 -0700
verilog reader use gzstream
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 8a0c8ce09087cceef36824de3656b5c7cea9f0f0
Author: James Cherry <cherry@parallaxsw.com>
Date: Mon Jan 13 18:02:40 2025 -0700
VerilogScanner::error
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 413093e46e523d90e45a4c56ecaa25e4457998aa
Author: James Cherry <cherry@parallaxsw.com>
Date: Fri Jan 10 18:27:53 2025 -0700
rm verilog_network
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit aef8358a8f44e556a3814e9ddd205e179bf2b3d7
Author: James Cherry <cherry@parallaxsw.com>
Date: Fri Jan 10 18:01:09 2025 -0700
rm verilog_reader except link
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit cfc34aa41a5fe1942867c73061ae483e36c74f54
Author: James Cherry <cherry@parallaxsw.com>
Date: Fri Jan 10 17:04:33 2025 -0700
verilog reader rm line_
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 62dd98b7cb800acc61192b0f326d4a3278e1a72d
Author: James Cherry <cherry@parallaxsw.com>
Date: Fri Jan 10 16:26:09 2025 -0700
verilog parse use location
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit ad6c26984526312134d03c0f39d3fcd63617efa4
Author: James Cherry <cherry@parallaxsw.com>
Date: Sat Jan 4 11:04:16 2025 -0800
verilog parse error
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 1bff12c8c49c847de015dd32042cccf7952a2060
Author: James Cherry <cherry@parallaxsw.com>
Date: Sat Jan 4 08:00:40 2025 -0800
attribute -> Attr
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit e8372df18a5374b2c9ca8f094a244d06c59a9f4e
Author: James Cherry <cherry@parallaxsw.com>
Date: Fri Jan 3 17:57:21 2025 -0800
verilog rm string_buf
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 785818f10108f689b4ea978a13d0131546f1a4e5
Author: James Cherry <cherry@parallaxsw.com>
Date: Fri Jan 3 16:10:10 2025 -0800
verilog parse use std::string
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 95265fc4ad30325f115eb69d10c77afe3f265701
Author: James Cherry <cherry@parallaxsw.com>
Date: Fri Jan 3 15:44:31 2025 -0800
verilog parser const char * -> string*
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit b80db6d98057363f90a9497b10073f84c2e7cc3d
Author: James Cherry <cherry@parallaxsw.com>
Date: Thu Jan 2 08:31:06 2025 -0800
bison warning
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit df3b61bf7d590c241ee513eacfb1c7dff2a450d8
Author: James Cherry <cherry@parallaxsw.com>
Date: Wed Jan 1 17:04:17 2025 -0800
verilog parse works
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 8b5a8fbb7042ceb58fbb24b836664a1da6028c45
Author: James Cherry <cherry@parallaxsw.com>
Date: Wed Jan 1 16:15:44 2025 -0800
rm VerilogParser.hh
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 07bc0cc9c160e9dbe705f4c359973cc35342e05e
Author: James Cherry <cherry@parallaxsw.com>
Date: Wed Jan 1 15:59:57 2025 -0800
verlog parse compiles
Signed-off-by: James Cherry <cherry@parallaxsw.com>
commit 8d32f5f3d5e6a252cdb2020c62742f01b1c66f63
Author: James Cherry <cherry@parallaxsw.com>
Date: Mon Dec 30 09:14:13 2024 -0800
verilog parser
Signed-off-by: James Cherry <cherry@parallaxsw.com>
Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry
parent
fc92c8411d
commit
cade6da64d
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@ -266,58 +266,60 @@ find_package(FLEX)
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find_package(BISON)
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# LibertyExpr scan/parse.
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flex_target(LibertyExprLex ${STA_HOME}/liberty/LibertyExprLex.ll ${CMAKE_CURRENT_BINARY_DIR}/LibertyExprLex.cc
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flex_target(LibertyExprLex ${STA_HOME}/liberty/LibertyExprLex.ll
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${CMAKE_CURRENT_BINARY_DIR}/LibertyExprLex.cc
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COMPILE_FLAGS --prefix=LibertyExprLex_)
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bison_target(LibertyExprParser ${STA_HOME}/liberty/LibertyExprParse.yy ${CMAKE_CURRENT_BINARY_DIR}/LibertyExprParse.cc
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bison_target(LibertyExprParse ${STA_HOME}/liberty/LibertyExprParse.yy
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${CMAKE_CURRENT_BINARY_DIR}/LibertyExprParse.cc
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COMPILE_FLAGS --name-prefix=LibertyExprParse_
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)
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add_flex_bison_dependency(LibertyExprLex LibertyExprParser)
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add_flex_bison_dependency(LibertyExprLex LibertyExprParse)
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# Liberty scan/parse.
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flex_target(LibertyLex ${STA_HOME}/liberty/LibertyLex.ll ${CMAKE_CURRENT_BINARY_DIR}/LibertyLex.cc
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COMPILE_FLAGS --prefix=LibertyLex_
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)
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bison_target(LibertyParser ${STA_HOME}/liberty/LibertyParse.yy ${CMAKE_CURRENT_BINARY_DIR}/LibertyParse.cc
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bison_target(LibertyParse ${STA_HOME}/liberty/LibertyParse.yy ${CMAKE_CURRENT_BINARY_DIR}/LibertyParse.cc
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COMPILE_FLAGS "--name-prefix=LibertyParse_ -v"
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)
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add_flex_bison_dependency(LibertyLex LibertyParser)
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add_flex_bison_dependency(LibertyLex LibertyParse)
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# Spef scan/parse.
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flex_target(SpefLex ${STA_HOME}/parasitics/SpefLex.ll ${CMAKE_CURRENT_BINARY_DIR}/SpefLex.cc
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COMPILE_FLAGS --prefix=SpefLex_
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)
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bison_target(SpefParser ${STA_HOME}/parasitics/SpefParse.yy ${CMAKE_CURRENT_BINARY_DIR}/SpefParse.cc
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bison_target(SpefParse ${STA_HOME}/parasitics/SpefParse.yy ${CMAKE_CURRENT_BINARY_DIR}/SpefParse.cc
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COMPILE_FLAGS --name-prefix=SpefParse_
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)
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add_flex_bison_dependency(SpefLex SpefParser)
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add_flex_bison_dependency(SpefLex SpefParse)
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# Verilog scan/parse.
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flex_target(VerilogLex ${STA_HOME}/verilog/VerilogLex.ll ${CMAKE_CURRENT_BINARY_DIR}/VerilogLex.cc
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COMPILE_FLAGS --prefix=VerilogLex_
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)
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bison_target(VerilogParser ${STA_HOME}/verilog/VerilogParse.yy ${CMAKE_CURRENT_BINARY_DIR}/VerilogParse.cc
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COMPILE_FLAGS --name-prefix=VerilogParse_
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)
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add_flex_bison_dependency(VerilogLex VerilogParser)
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flex_target(VerilogLex ${STA_HOME}/verilog/VerilogLex.ll
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${CMAKE_CURRENT_BINARY_DIR}/VerilogLex.cc)
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bison_target(VerilogParse ${STA_HOME}/verilog/VerilogParse.yy
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${CMAKE_CURRENT_BINARY_DIR}/VerilogParse.cc
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# centos7 bison 3.0.4 < 3.3.0 uses parser_class_name instead of api.parsr.class
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COMPILE_FLAGS -Wno-deprecated)
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add_flex_bison_dependency(VerilogLex VerilogParse)
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# Sdf scan/parse.
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flex_target(SdfLex ${STA_HOME}/sdf/SdfLex.ll ${CMAKE_CURRENT_BINARY_DIR}/SdfLex.cc
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COMPILE_FLAGS --prefix=SdfLex_
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)
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bison_target(SdfParser ${STA_HOME}/sdf/SdfParse.yy ${CMAKE_CURRENT_BINARY_DIR}/SdfParse.cc
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bison_target(SdfParse ${STA_HOME}/sdf/SdfParse.yy ${CMAKE_CURRENT_BINARY_DIR}/SdfParse.cc
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COMPILE_FLAGS --name-prefix=SdfParse_
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)
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add_flex_bison_dependency(SdfLex SdfParser)
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add_flex_bison_dependency(SdfLex SdfParse)
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# Saif scan/parse.
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flex_target(SaifLex ${STA_HOME}/power/SaifLex.ll ${CMAKE_CURRENT_BINARY_DIR}/SaifLex.cc
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COMPILE_FLAGS --prefix=SaifLex_
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)
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bison_target(SaifParser ${STA_HOME}/power/SaifParse.yy ${CMAKE_CURRENT_BINARY_DIR}/SaifParse.cc
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bison_target(SaifParse ${STA_HOME}/power/SaifParse.yy ${CMAKE_CURRENT_BINARY_DIR}/SaifParse.cc
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COMPILE_FLAGS --name-prefix=SaifParse_
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)
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add_flex_bison_dependency(SaifLex SaifParser)
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add_flex_bison_dependency(SaifLex SaifParse)
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################################################################
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@ -489,21 +491,21 @@ target_sources(OpenSTA
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${STA_TCL_INIT}
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${FLEX_LibertyExprLex_OUTPUTS}
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${BISON_LibertyExprParser_OUTPUTS}
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${BISON_LibertyExprParse_OUTPUTS}
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${FLEX_LibertyLex_OUTPUTS}
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${BISON_LibertyParser_OUTPUTS}
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${BISON_LibertyParse_OUTPUTS}
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${FLEX_SpefLex_OUTPUTS}
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${BISON_SpefParser_OUTPUTS}
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${BISON_SpefParse_OUTPUTS}
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${FLEX_SdfLex_OUTPUTS}
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${BISON_SdfParser_OUTPUTS}
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${BISON_SdfParse_OUTPUTS}
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${FLEX_VerilogLex_OUTPUTS}
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${BISON_VerilogParser_OUTPUTS}
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${BISON_VerilogParse_OUTPUTS}
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${FLEX_SaifLex_OUTPUTS}
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${BISON_SaifParser_OUTPUTS}
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${BISON_SaifParse_OUTPUTS}
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)
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target_link_libraries(OpenSTA
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@ -521,11 +523,14 @@ target_include_directories(OpenSTA
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PUBLIC
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include
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${TCL_INCLUDE_PATH}
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${FLEX_INCLUDE_DIRS}
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PRIVATE
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include/sta
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${STA_HOME}
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${CUDD_INCLUDE}
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# For flex to find location.hh
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${CMAKE_CURRENT_BINARY_DIR}
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)
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if (TCL_READLINE)
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@ -237,7 +237,7 @@ public:
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void deleteCellNetworkViews() override;
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void readNetlistBefore() override;
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void setLinkFunc(LinkNetworkFunc *link) override;
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void setLinkFunc(LinkNetworkFunc link) override;
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static ObjectId nextObjectId();
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// Used by external tools.
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@ -273,7 +273,7 @@ protected:
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ConcreteLibraryMap library_map_;
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Instance *top_instance_;
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NetSet constant_nets_[2]; // LogicValue::zero/one
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LinkNetworkFunc *link_func_;
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LinkNetworkFunc link_func_;
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CellNetworkViewMap cell_network_view_map_;
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static ObjectId object_id_;
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@ -27,6 +27,8 @@
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namespace sta {
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using std::function;
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class Report;
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class PatternMatch;
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class PinVisitor;
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@ -34,10 +36,8 @@ class PinVisitor;
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typedef Map<const char*, LibertyLibrary*, CharPtrLess> LibertyLibraryMap;
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// Link network function returns top level instance.
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// Return nullptr if link fails.
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typedef Instance *(LinkNetworkFunc)(const char *top_cell_name,
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bool make_black_boxes,
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Report *report,
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NetworkReader *network);
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typedef function<Instance* (const char *top_cell_name,
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bool make_black_boxes)> LinkNetworkFunc;
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typedef Map<const Net*, PinSet*> NetDrvrPinsMap;
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// The Network class defines the network API used by sta.
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@ -535,7 +535,7 @@ public:
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NetworkReader() {}
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// Called before reading a netlist to delete any previously linked network.
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virtual void readNetlistBefore() = 0;
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virtual void setLinkFunc(LinkNetworkFunc *link) = 0;
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virtual void setLinkFunc(LinkNetworkFunc link) = 0;
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virtual Library *makeLibrary(const char *name,
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const char *filename) = 0;
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virtual void deleteLibrary(Library *library) = 0;
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@ -43,6 +43,7 @@ class MinMax;
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class MinMaxAll;
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class RiseFallBoth;
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class RiseFall;
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class VerilogReader;
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class ReportPath;
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class CheckTiming;
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class DcalcAnalysisPt;
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@ -1439,6 +1440,7 @@ protected:
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CmdNamespace cmd_namespace_;
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Instance *current_instance_;
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Corner *cmd_corner_;
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VerilogReader *verilog_reader_;
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CheckTiming *check_timing_;
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CheckSlewLimits *check_slew_limits_;
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CheckFanoutLimits *check_fanout_limits_;
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@ -25,22 +25,19 @@ using std::string;
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string
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cellVerilogName(const char *sta_name);
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string
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instanceVerilogName(const char *sta_name,
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const char escape);
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instanceVerilogName(const char *sta_name);
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string
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netVerilogName(const char *sta_name,
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const char escape);
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netVerilogName(const char *sta_name);
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string
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portVerilogName(const char *sta_name,
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const char escape);
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portVerilogName(const char *sta_name);
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string
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moduleVerilogToSta(const char *sta_name);
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moduleVerilogToSta(const string *sta_name);
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string
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instanceVerilogToSta(const char *sta_name);
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instanceVerilogToSta(const string *sta_name);
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string
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netVerilogToSta(const char *sta_name);
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netVerilogToSta(const string *sta_name);
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string
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portVerilogToSta(const char *sta_name);
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portVerilogToSta(const string *sta_name);
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} // namespace
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@ -1951,7 +1951,7 @@ ConcreteNetwork::setTopInstance(Instance *top_inst)
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}
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void
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ConcreteNetwork::setLinkFunc(LinkNetworkFunc *link)
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ConcreteNetwork::setLinkFunc(LinkNetworkFunc link)
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{
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link_func_ = link;
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}
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|
|
@ -1964,7 +1964,7 @@ ConcreteNetwork::linkNetwork(const char *top_cell_name,
|
|||
if (link_func_) {
|
||||
clearConstantNets();
|
||||
deleteTopInstance();
|
||||
top_instance_ = link_func_(top_cell_name, make_black_boxes, report, this);
|
||||
top_instance_ = link_func_(top_cell_name, make_black_boxes);
|
||||
if (top_instance_)
|
||||
checkNetworkLibertyCorners();
|
||||
return top_instance_ != nullptr;
|
||||
|
|
|
|||
|
|
@ -23,56 +23,52 @@
|
|||
|
||||
namespace sta {
|
||||
|
||||
constexpr char verilog_escape = '\\';
|
||||
|
||||
static string
|
||||
staToVerilog(const char *sta_name,
|
||||
const char escape);
|
||||
staToVerilog(const char *sta_name);
|
||||
static string
|
||||
staToVerilog2(const char *sta_name,
|
||||
const char escape);
|
||||
staToVerilog2(const char *sta_name);
|
||||
static string
|
||||
verilogToSta(const char *verilog_name);
|
||||
verilogToSta(const string *verilog_name);
|
||||
|
||||
string
|
||||
cellVerilogName(const char *sta_name)
|
||||
{
|
||||
return staToVerilog(sta_name, '\\');
|
||||
return staToVerilog(sta_name);
|
||||
}
|
||||
|
||||
string
|
||||
instanceVerilogName(const char *sta_name,
|
||||
const char escape)
|
||||
instanceVerilogName(const char *sta_name)
|
||||
{
|
||||
return staToVerilog(sta_name, escape);
|
||||
return staToVerilog(sta_name);
|
||||
}
|
||||
|
||||
string
|
||||
netVerilogName(const char *sta_name,
|
||||
const char escape)
|
||||
netVerilogName(const char *sta_name)
|
||||
{
|
||||
bool is_bus;
|
||||
string bus_name;
|
||||
int index;
|
||||
parseBusName(sta_name, '[', ']', escape, is_bus, bus_name, index);
|
||||
parseBusName(sta_name, '[', ']', verilog_escape, is_bus, bus_name, index);
|
||||
if (is_bus) {
|
||||
string bus_vname = staToVerilog(bus_name.c_str(), escape);
|
||||
string bus_vname = staToVerilog(bus_name.c_str());
|
||||
string vname;
|
||||
stringPrint(vname, "%s[%d]", bus_vname.c_str(), index);
|
||||
return vname;
|
||||
}
|
||||
else
|
||||
return staToVerilog2(sta_name, escape);
|
||||
return staToVerilog2(sta_name);
|
||||
}
|
||||
|
||||
string
|
||||
portVerilogName(const char *sta_name,
|
||||
const char escape)
|
||||
portVerilogName(const char *sta_name)
|
||||
{
|
||||
return staToVerilog2(sta_name, escape);
|
||||
return staToVerilog2(sta_name);
|
||||
}
|
||||
|
||||
static string
|
||||
staToVerilog(const char *sta_name,
|
||||
const char escape)
|
||||
staToVerilog(const char *sta_name)
|
||||
{
|
||||
// Leave room for leading escape and trailing space if the name
|
||||
// needs to be escaped.
|
||||
|
|
@ -81,9 +77,9 @@ staToVerilog(const char *sta_name,
|
|||
bool escaped = false;
|
||||
for (const char *s = sta_name; *s ; s++) {
|
||||
char ch = s[0];
|
||||
if (ch == escape) {
|
||||
if (ch == verilog_escape) {
|
||||
char next_ch = s[1];
|
||||
if (next_ch == escape) {
|
||||
if (next_ch == verilog_escape) {
|
||||
escaped_name += ch;
|
||||
escaped_name += next_ch;
|
||||
s++;
|
||||
|
|
@ -108,8 +104,7 @@ staToVerilog(const char *sta_name,
|
|||
}
|
||||
|
||||
static string
|
||||
staToVerilog2(const char *sta_name,
|
||||
const char escape)
|
||||
staToVerilog2(const char *sta_name)
|
||||
{
|
||||
constexpr char bus_brkt_left = '[';
|
||||
constexpr char bus_brkt_right = ']';
|
||||
|
|
@ -120,9 +115,9 @@ staToVerilog2(const char *sta_name,
|
|||
bool escaped = false;
|
||||
for (const char *s = sta_name; *s ; s++) {
|
||||
char ch = s[0];
|
||||
if (ch == escape) {
|
||||
if (ch == verilog_escape) {
|
||||
char next_ch = s[1];
|
||||
if (next_ch == escape) {
|
||||
if (next_ch == verilog_escape) {
|
||||
escaped_name += ch;
|
||||
escaped_name += next_ch;
|
||||
s++;
|
||||
|
|
@ -151,58 +146,56 @@ staToVerilog2(const char *sta_name,
|
|||
////////////////////////////////////////////////////////////////
|
||||
|
||||
string
|
||||
moduleVerilogToSta(const char *module_name)
|
||||
moduleVerilogToSta(const string *module_name)
|
||||
{
|
||||
return verilogToSta(module_name);
|
||||
}
|
||||
|
||||
string
|
||||
instanceVerilogToSta(const char *inst_name)
|
||||
instanceVerilogToSta(const string *inst_name)
|
||||
{
|
||||
return verilogToSta(inst_name);
|
||||
}
|
||||
|
||||
string
|
||||
netVerilogToSta(const char *net_name)
|
||||
netVerilogToSta(const string *net_name)
|
||||
{
|
||||
return verilogToSta(net_name);
|
||||
}
|
||||
|
||||
string
|
||||
portVerilogToSta(const char *port_name)
|
||||
portVerilogToSta(const string *port_name)
|
||||
{
|
||||
return verilogToSta(port_name);
|
||||
}
|
||||
|
||||
static string
|
||||
verilogToSta(const char *verilog_name)
|
||||
verilogToSta(const string *verilog_name)
|
||||
{
|
||||
if (verilog_name && verilog_name[0] == '\\') {
|
||||
if (verilog_name->front() == '\\') {
|
||||
constexpr char divider = '/';
|
||||
constexpr char escape = '\\';
|
||||
constexpr char bus_brkt_left = '[';
|
||||
constexpr char bus_brkt_right = ']';
|
||||
|
||||
// Ignore leading '\'.
|
||||
verilog_name = &verilog_name[1];
|
||||
size_t verilog_name_length = strlen(verilog_name);
|
||||
if (isspace(verilog_name[verilog_name_length - 1]))
|
||||
size_t verilog_name_length = verilog_name->size();
|
||||
if (isspace(verilog_name->back()))
|
||||
verilog_name_length--;
|
||||
string sta_name;
|
||||
for (size_t i = 0; i < verilog_name_length; i++) {
|
||||
char ch = verilog_name[i];
|
||||
// Ignore leading '\'.
|
||||
for (size_t i = 1; i < verilog_name_length; i++) {
|
||||
char ch = verilog_name->at(i);
|
||||
if (ch == bus_brkt_left
|
||||
|| ch == bus_brkt_right
|
||||
|| ch == divider
|
||||
|| ch == escape)
|
||||
|| ch == verilog_escape)
|
||||
// Escape bus brackets, dividers and escapes.
|
||||
sta_name += escape;
|
||||
sta_name += verilog_escape;
|
||||
sta_name += ch;
|
||||
}
|
||||
return sta_name;
|
||||
}
|
||||
else
|
||||
return string(verilog_name);
|
||||
return string(*verilog_name);
|
||||
}
|
||||
|
||||
} // namespace
|
||||
|
|
|
|||
|
|
@ -218,7 +218,7 @@ VcdCountReader::makeVar(const VcdScope &scope,
|
|||
// Strip the scope from the name.
|
||||
string var_scoped = path_name.substr(scope_length + 1);
|
||||
if (width == 1) {
|
||||
string pin_name = netVerilogToSta(var_scoped.c_str());
|
||||
string pin_name = netVerilogToSta(&var_scoped);
|
||||
addVarPin(pin_name, id, width, 0);
|
||||
}
|
||||
else {
|
||||
|
|
@ -228,7 +228,7 @@ VcdCountReader::makeVar(const VcdScope &scope,
|
|||
parseBusName(var_scoped.c_str(), '[', ']', '\\',
|
||||
is_bus, is_range, bus_name, from, to, subscript_wild);
|
||||
if (is_bus) {
|
||||
string sta_bus_name = netVerilogToSta(bus_name.c_str());
|
||||
string sta_bus_name = netVerilogToSta(&bus_name);
|
||||
int bit_idx = 0;
|
||||
if (to < from) {
|
||||
for (int bus_bit = to; bus_bit <= from; bus_bit++) {
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@
|
|||
#include "SdcNetwork.hh"
|
||||
#include "MakeConcreteNetwork.hh"
|
||||
#include "PortDirection.hh"
|
||||
#include "VerilogReader.hh"
|
||||
#include "verilog/VerilogReader.hh"
|
||||
#include "Graph.hh"
|
||||
#include "GraphCmp.hh"
|
||||
#include "Sdc.hh"
|
||||
|
|
@ -235,9 +235,6 @@ initSta()
|
|||
void
|
||||
deleteAllMemory()
|
||||
{
|
||||
// Verilog modules refer to the network in the sta so it has
|
||||
// to deleted before the sta.
|
||||
deleteVerilogReader();
|
||||
Sta *sta = Sta::sta();
|
||||
if (sta) {
|
||||
delete sta;
|
||||
|
|
@ -257,6 +254,8 @@ Sta *Sta::sta_;
|
|||
Sta::Sta() :
|
||||
StaState(),
|
||||
current_instance_(nullptr),
|
||||
cmd_corner_(nullptr),
|
||||
verilog_reader_(nullptr),
|
||||
check_timing_(nullptr),
|
||||
check_slew_limits_(nullptr),
|
||||
check_fanout_limits_(nullptr),
|
||||
|
|
@ -514,6 +513,9 @@ Sta::sta()
|
|||
|
||||
Sta::~Sta()
|
||||
{
|
||||
// Verilog modules refer to the network in the sta so it has
|
||||
// to deleted before the network.
|
||||
delete verilog_reader_;
|
||||
// Delete "top down" to minimize chance of referencing deleted memory.
|
||||
delete check_slew_limits_;
|
||||
delete check_fanout_limits_;
|
||||
|
|
@ -728,8 +730,10 @@ Sta::readVerilog(const char *filename)
|
|||
{
|
||||
NetworkReader *network = networkReader();
|
||||
if (network) {
|
||||
if (verilog_reader_ == nullptr)
|
||||
verilog_reader_ = new VerilogReader(network);
|
||||
readNetlistBefore();
|
||||
return readVerilogFile(filename, network);
|
||||
return verilog_reader_->read(filename);
|
||||
}
|
||||
else
|
||||
return false;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# Tests whether Verilog attributes can be parsed and retrieved correctly
|
||||
# verilog attribute parse/raccess
|
||||
read_liberty ../examples/sky130hd_tt.lib.gz
|
||||
read_verilog verilog_attribute.v
|
||||
link_design counter
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
// centos7 flex 2.5.37
|
||||
// workaround for flex versions that insert register declarations
|
||||
#if !(YY_FLEX_MAJOR_VERSION >= 2 && YY_FLEX_MINOR_VERSION >= 6) && __cplusplus > 199711L
|
||||
#define register
|
||||
|
|
|
|||
|
|
@ -0,0 +1,213 @@
|
|||
// ============================================================================
|
||||
// gzstream, C++ iostream classes wrapping the zlib compression library.
|
||||
// Copyright (C) 2001 Deepak Bandyopadhyay, Lutz Kettner
|
||||
//
|
||||
// This library is free software; you can redistribute it and/or
|
||||
// modify it under the terms of the GNU Lesser General Public
|
||||
// License as published by the Free Software Foundation; either
|
||||
// version 2.1 of the License, or (at your option) any later version.
|
||||
//
|
||||
// This library is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
// Lesser General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU Lesser General Public
|
||||
// License along with this library; if not, write to the Free Software
|
||||
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
// ============================================================================
|
||||
//
|
||||
// File : gzstream.h
|
||||
// Revision : $Revision: 1.5 $
|
||||
// Revision_date : $Date: 2002/04/26 23:30:15 $
|
||||
// Author(s) : Deepak Bandyopadhyay, Lutz Kettner
|
||||
//
|
||||
// Standard streambuf implementation following Nicolai Josuttis, "The
|
||||
// Standard C++ Library".
|
||||
// ============================================================================
|
||||
|
||||
// downloaded from https://gist.github.com/piti118/1508048
|
||||
|
||||
#pragma once
|
||||
|
||||
// standard C++ with new header file names and std:: namespace
|
||||
#include <iostream>
|
||||
#include <fstream>
|
||||
#include <zlib.h>
|
||||
#include <string>
|
||||
#include <cstring>
|
||||
|
||||
namespace gzstream {
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Internal classes to implement gzstream. See below for user classes.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
class gzstreambuf : public std::streambuf {
|
||||
private:
|
||||
static const int bufferSize = 47+256; // size of data buff
|
||||
// totals 512 bytes under g++ for igzstream at the end.
|
||||
|
||||
gzFile file; // file handle for compressed file
|
||||
char buffer[bufferSize]; // data buffer
|
||||
char opened; // open/close state of stream
|
||||
int mode; // I/O mode
|
||||
|
||||
|
||||
int flush_buffer() {
|
||||
// Separate the writing of the buffer from overflow() and
|
||||
// sync() operation.
|
||||
int w = pptr() - pbase();
|
||||
if ( gzwrite( file, pbase(), w) != w)
|
||||
return EOF;
|
||||
pbump( -w);
|
||||
return w;
|
||||
}
|
||||
public:
|
||||
gzstreambuf() : opened(0) {
|
||||
setp( buffer, buffer + (bufferSize-1));
|
||||
setg( buffer + 4, // beginning of putback area
|
||||
buffer + 4, // read position
|
||||
buffer + 4); // end position
|
||||
// ASSERT: both input & output capabilities will not be used together
|
||||
}
|
||||
int is_open() { return opened; }
|
||||
|
||||
~gzstreambuf() { close(); }
|
||||
gzstreambuf* open( const char* name, int open_mode) {
|
||||
if ( is_open())
|
||||
return (gzstreambuf*)0;
|
||||
mode = open_mode;
|
||||
// no append nor read/write mode
|
||||
if ((mode & std::ios::ate) || (mode & std::ios::app)
|
||||
|| ((mode & std::ios::in) && (mode & std::ios::out)))
|
||||
return (gzstreambuf*)0;
|
||||
char fmode[10];
|
||||
char* fmodeptr = fmode;
|
||||
if ( mode & std::ios::in)
|
||||
*fmodeptr++ = 'r';
|
||||
else if ( mode & std::ios::out)
|
||||
*fmodeptr++ = 'w';
|
||||
*fmodeptr++ = 'b';
|
||||
*fmodeptr = '\0';
|
||||
file = gzopen( name, fmode);
|
||||
if (file == 0)
|
||||
return (gzstreambuf*)0;
|
||||
opened = 1;
|
||||
return this;
|
||||
}
|
||||
|
||||
gzstreambuf * close() {
|
||||
if ( is_open()) {
|
||||
sync();
|
||||
opened = 0;
|
||||
if ( gzclose( file) == Z_OK)
|
||||
return this;
|
||||
}
|
||||
return (gzstreambuf*)0;
|
||||
}
|
||||
|
||||
virtual int underflow() { // used for input buffer only
|
||||
if ( gptr() && ( gptr() < egptr()))
|
||||
return * reinterpret_cast<unsigned char *>( gptr());
|
||||
|
||||
if ( ! (mode & std::ios::in) || ! opened)
|
||||
return EOF;
|
||||
// Josuttis' implementation of inbuf
|
||||
int n_putback = gptr() - eback();
|
||||
if ( n_putback > 4)
|
||||
n_putback = 4;
|
||||
memcpy( buffer + (4 - n_putback), gptr() - n_putback, n_putback);
|
||||
|
||||
int num = gzread( file, buffer+4, bufferSize-4);
|
||||
if (num <= 0) // ERROR or EOF
|
||||
return EOF;
|
||||
|
||||
// reset buffer pointers
|
||||
setg( buffer + (4 - n_putback), // beginning of putback area
|
||||
buffer + 4, // read position
|
||||
buffer + 4 + num); // end of buffer
|
||||
|
||||
// return next character
|
||||
return * reinterpret_cast<unsigned char *>( gptr());
|
||||
}
|
||||
|
||||
virtual int overflow( int c=EOF) { // used for output buffer only
|
||||
if ( ! ( mode & std::ios::out) || ! opened)
|
||||
return EOF;
|
||||
if (c != EOF) {
|
||||
*pptr() = c;
|
||||
pbump(1);
|
||||
}
|
||||
if ( flush_buffer() == EOF)
|
||||
return EOF;
|
||||
return c;
|
||||
}
|
||||
|
||||
virtual int sync() {
|
||||
// Changed to use flush_buffer() instead of overflow( EOF)
|
||||
// which caused improper behavior with std::endl and flush(),
|
||||
// bug reported by Vincent Ricard.
|
||||
if ( pptr() && pptr() > pbase()) {
|
||||
if ( flush_buffer() == EOF)
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
};
|
||||
|
||||
class gzstreambase : virtual public std::ios {
|
||||
protected:
|
||||
gzstreambuf buf;
|
||||
public:
|
||||
|
||||
gzstreambase() { init(&buf); }
|
||||
gzstreambase( const char* name, int mode) {
|
||||
init( &buf);
|
||||
open( name, mode);
|
||||
}
|
||||
~gzstreambase() {
|
||||
buf.close();
|
||||
}
|
||||
void open( const char* name, int open_mode) {
|
||||
if ( ! buf.open( name, open_mode))
|
||||
clear( rdstate() | std::ios::badbit);
|
||||
}
|
||||
|
||||
void close() {
|
||||
if ( buf.is_open())
|
||||
if ( ! buf.close())
|
||||
clear( rdstate() | std::ios::badbit);
|
||||
}
|
||||
gzstreambuf* rdbuf() { return &buf; }
|
||||
};
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// User classes. Use igzstream and ogzstream analogously to ifstream and
|
||||
// ofstream respectively. They read and write files based on the gz*
|
||||
// function interface of the zlib. Files are compatible with gzip compression.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
class igzstream : public gzstreambase, public std::istream {
|
||||
public:
|
||||
igzstream() : std::istream( &buf) {}
|
||||
igzstream( const char* name, int open_mode = std::ios::in)
|
||||
: gzstreambase( name, open_mode), std::istream( &buf) {}
|
||||
gzstreambuf* rdbuf() { return gzstreambase::rdbuf(); }
|
||||
void open( const char* name, int open_mode = std::ios::in) {
|
||||
gzstreambase::open( name, open_mode);
|
||||
}
|
||||
};
|
||||
|
||||
class ogzstream : public gzstreambase, public std::ostream {
|
||||
public:
|
||||
ogzstream() : std::ostream( &buf) {}
|
||||
ogzstream( const char* name, int mode = std::ios::out)
|
||||
: gzstreambase( name, mode), std::ostream( &buf) {}
|
||||
gzstreambuf* rdbuf() { return gzstreambase::rdbuf(); }
|
||||
void open( const char* name, int open_mode = std::ios::out) {
|
||||
gzstreambase::open( name, open_mode);
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace GZSTREAM_NAMESPACE
|
||||
|
|
@ -17,14 +17,8 @@
|
|||
%module verilog
|
||||
|
||||
%{
|
||||
#include "VerilogReader.hh"
|
||||
#include "VerilogWriter.hh"
|
||||
#include "Sta.hh"
|
||||
|
||||
using sta::Sta;
|
||||
using sta::NetworkReader;
|
||||
using sta::readVerilogFile;
|
||||
|
||||
%}
|
||||
|
||||
%inline %{
|
||||
|
|
@ -35,22 +29,15 @@ read_verilog_cmd(const char *filename)
|
|||
return Sta::sta()->readVerilog(filename);
|
||||
}
|
||||
|
||||
void
|
||||
delete_verilog_reader()
|
||||
{
|
||||
deleteVerilogReader();
|
||||
}
|
||||
|
||||
void
|
||||
write_verilog_cmd(const char *filename,
|
||||
bool sort,
|
||||
bool include_pwr_gnd,
|
||||
CellSeq *remove_cells)
|
||||
{
|
||||
Sta *sta = Sta::sta();
|
||||
// This does NOT want the SDC (cmd) network because it wants
|
||||
// to see the sta internal names.
|
||||
Network *network = sta->network();
|
||||
Network *network = Sta::sta()->network();
|
||||
writeVerilog(filename, sort, include_pwr_gnd, remove_cells, network);
|
||||
delete remove_cells;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,4 @@
|
|||
%{
|
||||
|
||||
// OpenSTA, Static Timing Analyzer
|
||||
// Copyright (c) 2024, Parallax Software, Inc.
|
||||
//
|
||||
|
|
@ -16,29 +15,31 @@
|
|||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
#include "util/FlexDisableRegister.hh"
|
||||
#include "Debug.hh"
|
||||
#include "VerilogNamespace.hh"
|
||||
#include "verilog/VerilogReader.hh"
|
||||
#include "verilog/VerilogReaderPvt.hh"
|
||||
#include "VerilogParse.hh"
|
||||
#include "verilog/VerilogScanner.hh"
|
||||
#include "util/FlexDisableRegister.hh"
|
||||
|
||||
#define YY_NO_INPUT
|
||||
#undef YY_DECL
|
||||
#define YY_DECL \
|
||||
int \
|
||||
sta::VerilogScanner::yylex(sta::VerilogParse::semantic_type *const yylval, \
|
||||
sta::VerilogParse::location_type *loc)
|
||||
|
||||
int verilog_line = 1;
|
||||
static std::string string_buf;
|
||||
// update location on matching
|
||||
#define YY_USER_ACTION loc->step(); loc->columns(yyleng);
|
||||
|
||||
void
|
||||
verilogFlushBuffer()
|
||||
{
|
||||
YY_FLUSH_BUFFER;
|
||||
}
|
||||
typedef sta::VerilogParse::token token;
|
||||
|
||||
%}
|
||||
|
||||
/* %option debug */
|
||||
%option c++
|
||||
%option yyclass="sta::VerilogScanner"
|
||||
%option noyywrap
|
||||
%option nounput
|
||||
%option never-interactive
|
||||
%option stack
|
||||
|
||||
%x COMMENT
|
||||
%x QSTRING
|
||||
|
|
@ -54,119 +55,126 @@ ID_TOKEN {ID_ESCAPED_TOKEN}|{ID_ALPHA_TOKEN}
|
|||
%%
|
||||
|
||||
^[ \t]*`.*{EOL} { /* Macro definition. */
|
||||
sta::verilog_reader->incrLine();
|
||||
loc->lines();
|
||||
loc->step();
|
||||
}
|
||||
|
||||
"//"[^\n]*{EOL} { /* Single line comment. */
|
||||
sta::verilog_reader->incrLine();
|
||||
loc->lines();
|
||||
loc->step();
|
||||
}
|
||||
|
||||
"/*" { BEGIN COMMENT; }
|
||||
<COMMENT>{
|
||||
.
|
||||
|
||||
{EOL} { sta::verilog_reader->incrLine(); }
|
||||
{EOL} {
|
||||
loc->lines();
|
||||
loc->step();
|
||||
}
|
||||
|
||||
"*/" { BEGIN INITIAL; }
|
||||
|
||||
<<EOF>> {
|
||||
VerilogParse_error("unterminated comment");
|
||||
error("unterminated comment");
|
||||
BEGIN(INITIAL);
|
||||
yyterminate();
|
||||
}
|
||||
}
|
||||
|
||||
{SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[bB][01_xz]+ {
|
||||
VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
|
||||
return CONSTANT;
|
||||
yylval->constant = new string(yytext);
|
||||
return token::CONSTANT;
|
||||
}
|
||||
|
||||
{SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[oO][0-7_xz]+ {
|
||||
VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
|
||||
return CONSTANT;
|
||||
yylval->constant = new string(yytext);
|
||||
return token::CONSTANT;
|
||||
}
|
||||
|
||||
{SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[dD][0-9_]+ {
|
||||
VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
|
||||
return CONSTANT;
|
||||
yylval->constant = new string(yytext);
|
||||
return token::CONSTANT;
|
||||
}
|
||||
|
||||
{SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[hH][0-9a-fA-F_xz]+ {
|
||||
VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
|
||||
return CONSTANT;
|
||||
yylval->constant = new string(yytext);
|
||||
return token::CONSTANT;
|
||||
}
|
||||
|
||||
{SIGN}?[0-9]+ {
|
||||
VerilogParse_lval.ival = atol(VerilogLex_text);
|
||||
return INT;
|
||||
yylval->ival = atol(yytext);
|
||||
return token::INT;
|
||||
}
|
||||
|
||||
":"|"."|"{"|"}"|"["|"]"|","|"*"|";"|"="|"-"|"+"|"|"|"("|")" {
|
||||
return ((int) VerilogLex_text[0]);
|
||||
return ((int) yytext[0]);
|
||||
}
|
||||
|
||||
"(*" { return ATTRIBUTE_OPEN; }
|
||||
"*)" { return ATTRIBUTE_CLOSED; }
|
||||
assign { return ASSIGN; }
|
||||
endmodule { return ENDMODULE; }
|
||||
inout { return INOUT; }
|
||||
input { return INPUT; }
|
||||
module { return MODULE; }
|
||||
output { return OUTPUT; }
|
||||
parameter { return PARAMETER; }
|
||||
defparam { return DEFPARAM; }
|
||||
reg { return REG; }
|
||||
supply0 { return SUPPLY0; }
|
||||
supply1 { return SUPPLY1; }
|
||||
tri { return TRI; }
|
||||
wand { return WAND; }
|
||||
wire { return WIRE; }
|
||||
wor { return WOR; }
|
||||
"(*" { return token::ATTR_OPEN; }
|
||||
"*)" { return token::ATTR_CLOSED; }
|
||||
assign { return token::ASSIGN; }
|
||||
endmodule { return token::ENDMODULE; }
|
||||
inout { return token::INOUT; }
|
||||
input { return token::INPUT; }
|
||||
module { return token::MODULE; }
|
||||
output { return token::OUTPUT; }
|
||||
parameter { return token::PARAMETER; }
|
||||
defparam { return token::DEFPARAM; }
|
||||
reg { return token::REG; }
|
||||
supply0 { return token::SUPPLY0; }
|
||||
supply1 { return token::SUPPLY1; }
|
||||
tri { return token::TRI; }
|
||||
wand { return token::WAND; }
|
||||
wire { return token::WIRE; }
|
||||
wor { return token::WOR; }
|
||||
|
||||
{ID_TOKEN}("."{ID_TOKEN})* {
|
||||
VerilogParse_lval.string = sta::stringCopy(VerilogLex_text);
|
||||
return ID;
|
||||
yylval->string = new string(yytext, yyleng);
|
||||
return token::ID;
|
||||
}
|
||||
|
||||
{EOL} { sta::verilog_reader->incrLine(); }
|
||||
{EOL} {
|
||||
loc->lines();
|
||||
loc->step();
|
||||
}
|
||||
|
||||
{BLANK} { /* ignore blanks */ }
|
||||
|
||||
\" {
|
||||
string_buf.erase();
|
||||
yylval->string = new string;
|
||||
BEGIN(QSTRING);
|
||||
}
|
||||
|
||||
<QSTRING>\" {
|
||||
BEGIN(INITIAL);
|
||||
VerilogParse_lval.string = sta::stringCopy(string_buf.c_str());
|
||||
return STRING;
|
||||
return token::STRING;
|
||||
}
|
||||
|
||||
<QSTRING>{EOL} {
|
||||
VerilogParse_error("unterminated string constant");
|
||||
error("unterminated quoted string");
|
||||
BEGIN(INITIAL);
|
||||
VerilogParse_lval.string = sta::stringCopy(string_buf.c_str());
|
||||
return STRING;
|
||||
return token::STRING;
|
||||
}
|
||||
|
||||
<QSTRING>\\{EOL} {
|
||||
/* Line continuation. */
|
||||
sta::verilog_reader->incrLine();
|
||||
loc->lines();
|
||||
loc->step();
|
||||
}
|
||||
|
||||
<QSTRING>[^\r\n\"]+ {
|
||||
/* Anything return or double quote */
|
||||
string_buf += VerilogLex_text;
|
||||
/* Anything return token::or double quote */
|
||||
*yylval->string += yytext;
|
||||
}
|
||||
|
||||
<QSTRING><<EOF>> {
|
||||
VerilogParse_error("unterminated string constant");
|
||||
error("unterminated string constant");
|
||||
BEGIN(INITIAL);
|
||||
yyterminate();
|
||||
}
|
||||
|
||||
/* Send out of bound characters to parser. */
|
||||
. { return (int) VerilogLex_text[0]; }
|
||||
. { return (int) yytext[0]; }
|
||||
|
||||
%%
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
%{
|
||||
|
||||
// OpenSTA, Static Timing Analyzer
|
||||
// Copyright (c) 2024, Parallax Software, Inc.
|
||||
//
|
||||
|
|
@ -16,26 +14,67 @@
|
|||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
%require "3.0"
|
||||
%skeleton "lalr1.cc"
|
||||
%debug
|
||||
%defines
|
||||
%define api.namespace {sta}
|
||||
|
||||
// bison 3.0.4 for centos7
|
||||
%define parser_class_name {VerilogParse}
|
||||
// bison 3.3.2
|
||||
//%define api.parser.class {VerilogParse}
|
||||
|
||||
%code requires {
|
||||
namespace sta {
|
||||
class VerilogReadcer;
|
||||
class VerilogScanner;
|
||||
}
|
||||
}
|
||||
|
||||
%locations
|
||||
|
||||
%parse-param { VerilogScanner *scanner }
|
||||
%parse-param { VerilogReader *reader }
|
||||
|
||||
%{
|
||||
#include <cstdlib>
|
||||
#include <string>
|
||||
#include <iostream>
|
||||
|
||||
#include "Report.hh"
|
||||
#include "PortDirection.hh"
|
||||
#include "verilog/VerilogReader.hh"
|
||||
#include "verilog/VerilogReaderPvt.hh"
|
||||
#include "VerilogReader.hh"
|
||||
|
||||
int VerilogLex_lex();
|
||||
#define VerilogParse_lex VerilogLex_lex
|
||||
// Use yacc generated parser errors.
|
||||
#define YYERROR_VERBOSE
|
||||
|
||||
#include "verilog/VerilogScanner.hh"
|
||||
%}
|
||||
|
||||
%union{
|
||||
%code {
|
||||
|
||||
#undef yylex
|
||||
#define yylex scanner->yylex
|
||||
|
||||
// warning: variable 'yynerrs_' set but not used
|
||||
#pragma GCC diagnostic ignored "-Wunused-but-set-variable"
|
||||
|
||||
#define loc_line(loc) loc.begin.line
|
||||
|
||||
void
|
||||
sta::VerilogParse::error(const location_type &loc,
|
||||
const string &msg)
|
||||
{
|
||||
reader->report()->fileError(164,reader->filename(),loc.begin.line,"%s",msg.c_str());
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
%define parse.assert
|
||||
|
||||
%union {
|
||||
int ival;
|
||||
const char *string;
|
||||
const char *constant;
|
||||
const char *attribute_spec_value;
|
||||
std::string *string;
|
||||
std::string *constant;
|
||||
std::string *attr_spec_value;
|
||||
sta::VerilogModule *module;
|
||||
sta::VerilogStmt *stmt;
|
||||
sta::VerilogStmtSeq *stmt_seq;
|
||||
|
|
@ -47,26 +86,25 @@ int VerilogLex_lex();
|
|||
sta::VerilogNet *net;
|
||||
sta::VerilogNetBitSelect *net_bit;
|
||||
sta::VerilogNetSeq *nets;
|
||||
sta::VerilogAttributeEntry *attribute_entry;
|
||||
sta::VerilogAttributeEntrySeq *attribute_seq;
|
||||
sta::VerilogAttributeStmt *attribute_stmt;
|
||||
sta::VerilogAttributeStmtSeq *attribute_stmt_seq;
|
||||
sta::VerilogAttrEntry *attr_entry;
|
||||
sta::VerilogAttrEntrySeq *attr_seq;
|
||||
sta::VerilogAttrStmt *attr_stmt;
|
||||
sta::VerilogAttrStmtSeq *attr_stmt_seq;
|
||||
}
|
||||
|
||||
%token INT CONSTANT ID STRING MODULE ENDMODULE ASSIGN PARAMETER DEFPARAM
|
||||
%token WIRE WAND WOR TRI INPUT OUTPUT INOUT SUPPLY1 SUPPLY0 REG
|
||||
%token ATTRIBUTE_OPEN ATTRIBUTE_CLOSED
|
||||
%token ATTR_OPEN ATTR_CLOSED
|
||||
|
||||
%left '-' '+'
|
||||
%left '*' '/'
|
||||
%left NEG /* negation--unary minus */
|
||||
|
||||
%type <string> ID STRING
|
||||
%type <string> ID STRING CONSTANT
|
||||
%type <ival> WIRE WAND WOR TRI INPUT OUTPUT INOUT SUPPLY1 SUPPLY0
|
||||
%type <ival> ATTRIBUTE_OPEN ATTRIBUTE_CLOSED
|
||||
%type <ival> INT parameter_exprs parameter_expr module_begin
|
||||
%type <constant> CONSTANT
|
||||
%type <attribute_spec_value> attr_spec_value
|
||||
%type <ival> ATTR_OPEN ATTR_CLOSED
|
||||
%type <ival> INT parameter_exprs parameter_expr
|
||||
%type <string> attr_spec_value
|
||||
%type <port_type> dcl_type port_dcl_type
|
||||
%type <stmt> stmt declaration instance parameter parameter_dcls parameter_dcl
|
||||
%type <stmt> defparam param_values param_value port_dcl
|
||||
|
|
@ -79,16 +117,18 @@ int VerilogLex_lex();
|
|||
%type <net> inst_named_pin net_named net_expr_concat
|
||||
%type <nets> port_list port_refs inst_ordered_pins
|
||||
%type <nets> inst_named_pins net_exprs inst_pins
|
||||
%type <attribute_entry> attr_spec
|
||||
%type <attribute_seq> attr_specs
|
||||
%type <attribute_stmt> attribute_instance
|
||||
%type <attribute_stmt_seq> attribute_instance_seq
|
||||
%type <attr_entry> attr_spec
|
||||
%type <attr_seq> attr_specs
|
||||
%type <attr_stmt> attr_instance
|
||||
%type <attr_stmt_seq> attr_instance_seq
|
||||
|
||||
// Used by error recovery.
|
||||
%destructor { delete $$; } STRING
|
||||
%destructor { delete $$; } CONSTANT
|
||||
%destructor { delete $$; } attr_spec_value
|
||||
|
||||
%start file
|
||||
|
||||
%{
|
||||
%}
|
||||
|
||||
%%
|
||||
|
||||
file:
|
||||
|
|
@ -100,20 +140,15 @@ modules:
|
|||
| modules module
|
||||
;
|
||||
|
||||
module_begin:
|
||||
MODULE { $<ival>$ = sta::verilog_reader->line(); }
|
||||
{ $$ = $<ival>2; }
|
||||
;
|
||||
|
||||
module:
|
||||
attribute_instance_seq module_begin ID ';' stmts ENDMODULE
|
||||
{ sta::verilog_reader->makeModule($3, new sta::VerilogNetSeq, $5, $1, $2);}
|
||||
| attribute_instance_seq module_begin ID '(' ')' ';' stmts ENDMODULE
|
||||
{ sta::verilog_reader->makeModule($3, new sta::VerilogNetSeq, $7, $1, $2);}
|
||||
| attribute_instance_seq module_begin ID '(' port_list ')' ';' stmts ENDMODULE
|
||||
{ sta::verilog_reader->makeModule($3, $5, $8, $1, $2); }
|
||||
| attribute_instance_seq module_begin ID '(' port_dcls ')' ';' stmts ENDMODULE
|
||||
{ sta::verilog_reader->makeModule($3, $5, $8, $1, $2); }
|
||||
attr_instance_seq MODULE ID ';' stmts ENDMODULE
|
||||
{ reader->makeModule($3, new sta::VerilogNetSeq,$5, $1, loc_line(@2));}
|
||||
| attr_instance_seq MODULE ID '(' ')' ';' stmts ENDMODULE
|
||||
{ reader->makeModule($3, new sta::VerilogNetSeq,$7, $1, loc_line(@2));}
|
||||
| attr_instance_seq MODULE ID '(' port_list ')' ';' stmts ENDMODULE
|
||||
{ reader->makeModule($3, $5, $8, $1, loc_line(@2)); }
|
||||
| attr_instance_seq MODULE ID '(' port_dcls ')' ';' stmts ENDMODULE
|
||||
{ reader->makeModule($3, $5, $8, $1, loc_line(@2)); }
|
||||
;
|
||||
|
||||
port_list:
|
||||
|
|
@ -128,15 +163,15 @@ port_list:
|
|||
port:
|
||||
port_expr
|
||||
| '.' ID '(' ')'
|
||||
{ $$=sta::verilog_reader->makeNetNamedPortRefScalar($2, NULL);}
|
||||
{ $$ = reader->makeNetNamedPortRefScalar($2, nullptr);}
|
||||
| '.' ID '(' port_expr ')'
|
||||
{ $$=sta::verilog_reader->makeNetNamedPortRefScalar($2, $4);}
|
||||
{ $$ = reader->makeNetNamedPortRefScalar($2, $4);}
|
||||
;
|
||||
|
||||
port_expr:
|
||||
port_ref
|
||||
| '{' port_refs '}'
|
||||
{ $$ = sta::verilog_reader->makeNetConcat($2); } ;
|
||||
{ $$ = reader->makeNetConcat($2); } ;
|
||||
|
||||
port_refs:
|
||||
port_ref
|
||||
|
|
@ -171,12 +206,10 @@ port_dcls:
|
|||
;
|
||||
|
||||
port_dcl:
|
||||
attribute_instance_seq port_dcl_type
|
||||
{ $<ival>$ = sta::verilog_reader->line(); } dcl_arg
|
||||
{ $$ = sta::verilog_reader->makeDcl($2, $4, $1, $<ival>3); }
|
||||
| attribute_instance_seq port_dcl_type
|
||||
{ $<ival>$ = sta::verilog_reader->line(); } '[' INT ':' INT ']' dcl_arg
|
||||
{ $$ = sta::verilog_reader->makeDclBus($2, $5, $7, $9, $1, $<ival>3); }
|
||||
attr_instance_seq port_dcl_type dcl_arg
|
||||
{ $$ = reader->makeDcl($2, $3, $1, loc_line(@2)); }
|
||||
| attr_instance_seq port_dcl_type '[' INT ':' INT ']' dcl_arg
|
||||
{ $$ = reader->makeDclBus($2, $4, $6, $8, $1, loc_line(@2)); }
|
||||
;
|
||||
|
||||
port_dcl_type:
|
||||
|
|
@ -210,7 +243,7 @@ stmt:
|
|||
| declaration
|
||||
| instance
|
||||
| error ';'
|
||||
{ yyerrok; $$ = NULL; }
|
||||
{ yyerrok; $$ = nullptr; }
|
||||
;
|
||||
|
||||
stmt_seq:
|
||||
|
|
@ -220,43 +253,32 @@ stmt_seq:
|
|||
/* Parameters are parsed and ignored. */
|
||||
parameter:
|
||||
PARAMETER parameter_dcls ';'
|
||||
{ $$ = NULL; }
|
||||
{ $$ = nullptr; }
|
||||
| PARAMETER '[' INT ':' INT ']' parameter_dcls ';'
|
||||
{ $$ = NULL; }
|
||||
{ $$ = nullptr; }
|
||||
;
|
||||
|
||||
parameter_dcls:
|
||||
parameter_dcl
|
||||
{ $$ = NULL; }
|
||||
{ $$ = nullptr; }
|
||||
| parameter_dcls ',' parameter_dcl
|
||||
{ $$ = NULL; }
|
||||
{ $$ = nullptr; }
|
||||
;
|
||||
|
||||
parameter_dcl:
|
||||
ID '=' parameter_expr
|
||||
{ sta::stringDelete($1);
|
||||
$$ = NULL;
|
||||
}
|
||||
{ delete $1; $$ = nullptr; }
|
||||
| ID '=' STRING
|
||||
{ sta::stringDelete($1);
|
||||
sta::stringDelete($3);
|
||||
$$ = NULL;
|
||||
}
|
||||
{ delete $1; delete $3; $$ = nullptr; }
|
||||
;
|
||||
|
||||
parameter_expr:
|
||||
ID
|
||||
{ sta::stringDelete($1);
|
||||
$$ = 0;
|
||||
}
|
||||
{ delete $1; $$ = 0; }
|
||||
| '`' ID
|
||||
{ sta::stringDelete($2);
|
||||
$$ = 0;
|
||||
}
|
||||
{ delete $2; $$ = 0; }
|
||||
| CONSTANT
|
||||
{ sta::stringDelete($1);
|
||||
$$ = 0;
|
||||
}
|
||||
{ delete $1; $$ = 0; }
|
||||
| INT
|
||||
| '-' parameter_expr %prec NEG
|
||||
{ $$ = - $2; }
|
||||
|
|
@ -274,34 +296,28 @@ parameter_expr:
|
|||
|
||||
defparam:
|
||||
DEFPARAM param_values ';'
|
||||
{ $$ = NULL; }
|
||||
{ $$ = nullptr; }
|
||||
;
|
||||
|
||||
param_values:
|
||||
param_value
|
||||
{ $$ = NULL; }
|
||||
{ $$ = nullptr; }
|
||||
| param_values ',' param_value
|
||||
{ $$ = NULL; }
|
||||
{ $$ = nullptr; }
|
||||
;
|
||||
|
||||
param_value:
|
||||
ID '=' parameter_expr
|
||||
{ sta::stringDelete($1);
|
||||
$$ = NULL;
|
||||
}
|
||||
{ delete $1; $$ = nullptr; }
|
||||
| ID '=' STRING
|
||||
{ sta::stringDelete($1);
|
||||
sta::stringDelete($3);
|
||||
$$ = NULL;
|
||||
}
|
||||
{ delete $1; delete $3; $$ = nullptr; }
|
||||
;
|
||||
|
||||
declaration:
|
||||
attribute_instance_seq dcl_type { $<ival>$ = sta::verilog_reader->line(); } dcl_args ';'
|
||||
{ $$ = sta::verilog_reader->makeDcl($2, $4, $1, $<ival>3); }
|
||||
| attribute_instance_seq dcl_type { $<ival>$ = sta::verilog_reader->line(); }
|
||||
'[' INT ':' INT ']' dcl_args ';'
|
||||
{ $$ = sta::verilog_reader->makeDclBus($2, $5, $7, $9, $1,$<ival>3); }
|
||||
attr_instance_seq dcl_type dcl_args ';'
|
||||
{ $$ = reader->makeDcl($2, $3, $1, loc_line(@2)); }
|
||||
| attr_instance_seq dcl_type '[' INT ':' INT ']' dcl_args ';'
|
||||
{ $$ = reader->makeDclBus($2, $4, $6, $8, $1,loc_line(@2)); }
|
||||
;
|
||||
|
||||
dcl_type:
|
||||
|
|
@ -329,9 +345,9 @@ dcl_args:
|
|||
|
||||
dcl_arg:
|
||||
ID
|
||||
{ $$ = sta::verilog_reader->makeDclArg($1); }
|
||||
{ $$ = reader->makeDclArg($1); }
|
||||
| net_assignment
|
||||
{ $$ = sta::verilog_reader->makeDclArg($1); }
|
||||
{ $$ = reader->makeDclArg($1); }
|
||||
;
|
||||
|
||||
continuous_assign:
|
||||
|
|
@ -349,8 +365,8 @@ net_assignments:
|
|||
;
|
||||
|
||||
net_assignment:
|
||||
net_assign_lhs { $<ival>$ = sta::verilog_reader->line(); } '=' net_expr
|
||||
{ $$ = sta::verilog_reader->makeAssign($1, $4, $<ival>2); }
|
||||
net_assign_lhs '=' net_expr
|
||||
{ $$ = reader->makeAssign($1, $3, loc_line(@1)); }
|
||||
;
|
||||
|
||||
net_assign_lhs:
|
||||
|
|
@ -359,11 +375,10 @@ net_assign_lhs:
|
|||
;
|
||||
|
||||
instance:
|
||||
attribute_instance_seq ID { $<ival>$ = sta::verilog_reader->line(); } ID '(' inst_pins ')' ';'
|
||||
{ $$ = sta::verilog_reader->makeModuleInst($2, $4, $6, $1, $<ival>3); }
|
||||
| attribute_instance_seq ID { $<ival>$ = sta::verilog_reader->line(); } parameter_values
|
||||
ID '(' inst_pins ')' ';'
|
||||
{ $$ = sta::verilog_reader->makeModuleInst($2, $5, $7, $1, $<ival>3); }
|
||||
attr_instance_seq ID ID '(' inst_pins ')' ';'
|
||||
{ $$ = reader->makeModuleInst($2, $3, $5, $1, loc_line(@2)); }
|
||||
| attr_instance_seq ID parameter_values ID '(' inst_pins ')' ';'
|
||||
{ $$ = reader->makeModuleInst($2, $4, $6, $1, loc_line(@2)); }
|
||||
;
|
||||
|
||||
parameter_values:
|
||||
|
|
@ -379,7 +394,7 @@ parameter_exprs:
|
|||
|
||||
inst_pins:
|
||||
// empty
|
||||
{ $$ = NULL; }
|
||||
{ $$ = nullptr; }
|
||||
| inst_ordered_pins
|
||||
| inst_named_pins
|
||||
;
|
||||
|
|
@ -409,23 +424,23 @@ inst_named_pins:
|
|||
inst_named_pin:
|
||||
// Scalar port.
|
||||
'.' ID '(' ')'
|
||||
{ $$ = sta::verilog_reader->makeNetNamedPortRefScalarNet($2); }
|
||||
{ $$ = reader->makeNetNamedPortRefScalarNet($2); }
|
||||
| '.' ID '(' ID ')'
|
||||
{ $$ = sta::verilog_reader->makeNetNamedPortRefScalarNet($2, $4); }
|
||||
{ $$ = reader->makeNetNamedPortRefScalarNet($2, $4); }
|
||||
| '.' ID '(' ID '[' INT ']' ')'
|
||||
{ $$ = sta::verilog_reader->makeNetNamedPortRefBitSelect($2, $4, $6); }
|
||||
{ $$ = reader->makeNetNamedPortRefBitSelect($2, $4, $6); }
|
||||
| '.' ID '(' named_pin_net_expr ')'
|
||||
{ $$ = sta::verilog_reader->makeNetNamedPortRefScalar($2, $4); }
|
||||
{ $$ = reader->makeNetNamedPortRefScalar($2, $4); }
|
||||
// Bus port bit select.
|
||||
| '.' ID '[' INT ']' '(' ')'
|
||||
{ $$ = sta::verilog_reader->makeNetNamedPortRefBit($2, $4, NULL); }
|
||||
{ $$ = reader->makeNetNamedPortRefBit($2, $4, nullptr); }
|
||||
| '.' ID '[' INT ']' '(' net_expr ')'
|
||||
{ $$ = sta::verilog_reader->makeNetNamedPortRefBit($2, $4, $7); }
|
||||
{ $$ = reader->makeNetNamedPortRefBit($2, $4, $7); }
|
||||
// Bus port part select.
|
||||
| '.' ID '[' INT ':' INT ']' '(' ')'
|
||||
{ $$ = sta::verilog_reader->makeNetNamedPortRefPart($2, $4, $6, NULL); }
|
||||
{ $$ = reader->makeNetNamedPortRefPart($2, $4, $6, nullptr); }
|
||||
| '.' ID '[' INT ':' INT ']' '(' net_expr ')'
|
||||
{ $$ = sta::verilog_reader->makeNetNamedPortRefPart($2, $4, $6, $9); }
|
||||
{ $$ = reader->makeNetNamedPortRefPart($2, $4, $6, $9); }
|
||||
;
|
||||
|
||||
named_pin_net_expr:
|
||||
|
|
@ -442,27 +457,27 @@ net_named:
|
|||
|
||||
net_scalar:
|
||||
ID
|
||||
{ $$ = sta::verilog_reader->makeNetScalar($1); }
|
||||
{ $$ = reader->makeNetScalar($1); }
|
||||
;
|
||||
|
||||
net_bit_select:
|
||||
ID '[' INT ']'
|
||||
{ $$ = sta::verilog_reader->makeNetBitSelect($1, $3); }
|
||||
{ $$ = reader->makeNetBitSelect($1, $3); }
|
||||
;
|
||||
|
||||
net_part_select:
|
||||
ID '[' INT ':' INT ']'
|
||||
{ $$ = sta::verilog_reader->makeNetPartSelect($1, $3, $5); }
|
||||
{ $$ = reader->makeNetPartSelect($1, $3, $5); }
|
||||
;
|
||||
|
||||
net_constant:
|
||||
CONSTANT
|
||||
{ $$ = sta::verilog_reader->makeNetConstant($1); }
|
||||
{ $$ = reader->makeNetConstant($1, loc_line(@1)); }
|
||||
;
|
||||
|
||||
net_expr_concat:
|
||||
'{' net_exprs '}'
|
||||
{ $$ = sta::verilog_reader->makeNetConcat($2); }
|
||||
{ $$ = reader->makeNetConcat($2); }
|
||||
;
|
||||
|
||||
net_exprs:
|
||||
|
|
@ -482,37 +497,32 @@ net_expr:
|
|||
| net_expr_concat
|
||||
;
|
||||
|
||||
attribute_instance_seq:
|
||||
attr_instance_seq:
|
||||
// empty
|
||||
{ $$ = new sta::VerilogAttributeStmtSeq; }
|
||||
| attribute_instance_seq attribute_instance
|
||||
{ $$ = new sta::VerilogAttrStmtSeq; }
|
||||
| attr_instance_seq attr_instance
|
||||
{ if ($2) $1->push_back($2); }
|
||||
;
|
||||
|
||||
attribute_instance:
|
||||
ATTRIBUTE_OPEN attr_specs ATTRIBUTE_CLOSED
|
||||
{ $$ = new sta::VerilogAttributeStmt($2); }
|
||||
attr_instance:
|
||||
ATTR_OPEN attr_specs ATTR_CLOSED
|
||||
{ $$ = new sta::VerilogAttrStmt($2); }
|
||||
;
|
||||
|
||||
attr_specs:
|
||||
attr_spec
|
||||
{ $$ = new sta::VerilogAttributeEntrySeq;
|
||||
{ $$ = new sta::VerilogAttrEntrySeq;
|
||||
$$->push_back($1);
|
||||
}
|
||||
| attr_specs ',' attr_spec
|
||||
| attr_specs ',' attr_spec
|
||||
{ $$->push_back($3); }
|
||||
;
|
||||
|
||||
attr_spec:
|
||||
ID
|
||||
{ $$ = new sta::VerilogAttributeEntry($1, "1");
|
||||
delete[] $1;
|
||||
}
|
||||
{ $$ = new sta::VerilogAttrEntry(*$1, "1"); delete $1; }
|
||||
| ID '=' attr_spec_value
|
||||
{ $$ = new sta::VerilogAttributeEntry($1, $3);
|
||||
delete[] $1;
|
||||
delete[] $3;
|
||||
}
|
||||
{ $$ = new sta::VerilogAttrEntry(*$1, *$3); delete $1; delete $3; }
|
||||
;
|
||||
|
||||
attr_spec_value:
|
||||
|
|
@ -521,7 +531,7 @@ attr_spec_value:
|
|||
| STRING
|
||||
{ $$ = $1; }
|
||||
| INT
|
||||
{ $$ = sta::stringCopy(std::to_string($1).c_str()); }
|
||||
{ $$ = new string(std::to_string($1)); }
|
||||
;
|
||||
|
||||
%%
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,292 @@
|
|||
// OpenSTA, Static Timing Analyzer
|
||||
// Copyright (c) 2024, Parallax Software, Inc.
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <string>
|
||||
|
||||
#include "StringSet.hh"
|
||||
#include "Vector.hh"
|
||||
#include "Map.hh"
|
||||
#include "NetworkClass.hh"
|
||||
|
||||
namespace sta {
|
||||
|
||||
class VerilogScanner;
|
||||
class VerilogParse;
|
||||
class Debug;
|
||||
class Report;
|
||||
class VerilogAttrEntry;
|
||||
class VerilogAttrStmt;
|
||||
class VerilogReader;
|
||||
class VerilogStmt;
|
||||
class VerilogNet;
|
||||
class VerilogNetScalar;
|
||||
class VerilogModule;
|
||||
class VerilogInst;
|
||||
class VerilogModuleInst;
|
||||
class VerilogLibertyInst;
|
||||
class VerilogDcl;
|
||||
class VerilogDclBus;
|
||||
class VerilogDclArg;
|
||||
class VerilogAssign;
|
||||
class VerilogNetConcat;
|
||||
class VerilogNetConstant;
|
||||
class VerilogNetBitSelect;
|
||||
class VerilogNetPartSelect;
|
||||
class StringRegistry;
|
||||
class VerilogBindingTbl;
|
||||
class VerilogNetNameIterator;
|
||||
class VerilogNetPortRef;
|
||||
class VerilogError;
|
||||
class LibertyCell;
|
||||
|
||||
typedef Map<Cell*, VerilogModule*> VerilogModuleMap;
|
||||
typedef Vector<VerilogStmt*> VerilogStmtSeq;
|
||||
typedef Vector<VerilogNet*> VerilogNetSeq;
|
||||
typedef Vector<VerilogDclArg*> VerilogDclArgSeq;
|
||||
typedef Vector<VerilogAttrStmt*> VerilogAttrStmtSeq;
|
||||
typedef Vector<VerilogAttrEntry*> VerilogAttrEntrySeq;
|
||||
typedef Vector<VerilogError*> VerilogErrorSeq;
|
||||
|
||||
using std::string;
|
||||
using std::vector;
|
||||
using std::set;
|
||||
|
||||
class VerilogReader
|
||||
{
|
||||
public:
|
||||
VerilogReader(NetworkReader *network);
|
||||
~VerilogReader();
|
||||
bool read(const char *filename);
|
||||
|
||||
void makeModule(const string *module_name,
|
||||
VerilogNetSeq *ports,
|
||||
VerilogStmtSeq *stmts,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
int line);
|
||||
void makeModule(const string *module_name,
|
||||
VerilogStmtSeq *port_dcls,
|
||||
VerilogStmtSeq *stmts,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
int line);
|
||||
VerilogDcl *makeDcl(PortDirection *dir,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
int line);
|
||||
VerilogDcl *makeDcl(PortDirection *dir,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
int line);
|
||||
VerilogDclArg *makeDclArg(const string *net_name);
|
||||
VerilogDclArg*makeDclArg(VerilogAssign *assign);
|
||||
VerilogDclBus *makeDclBus(PortDirection *dir,
|
||||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
int line);
|
||||
VerilogDclBus *makeDclBus(PortDirection *dir,
|
||||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
int line);
|
||||
VerilogInst *makeModuleInst(const string *module_name,
|
||||
const string *inst_name,
|
||||
VerilogNetSeq *pins,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
const int line);
|
||||
VerilogAssign *makeAssign(VerilogNet *lhs,
|
||||
VerilogNet *rhs,
|
||||
int line);
|
||||
VerilogNetScalar *makeNetScalar(const string *name);
|
||||
VerilogNetPortRef *makeNetNamedPortRefScalarNet(const string *port_vname);
|
||||
VerilogNetPortRef *makeNetNamedPortRefScalarNet(const string *port_name,
|
||||
const string *net_name);
|
||||
VerilogNetPortRef *makeNetNamedPortRefBitSelect(const string *port_name,
|
||||
const string *bus_name,
|
||||
int index);
|
||||
VerilogNetPortRef *makeNetNamedPortRefScalar(const string *port_name,
|
||||
VerilogNet *net);
|
||||
VerilogNetPortRef *makeNetNamedPortRefBit(const string *port_name,
|
||||
int index,
|
||||
VerilogNet *net);
|
||||
VerilogNetPortRef *makeNetNamedPortRefPart(const string *port_name,
|
||||
int from_index,
|
||||
int to_index,
|
||||
VerilogNet *net);
|
||||
VerilogNetConcat *makeNetConcat(VerilogNetSeq *nets);
|
||||
VerilogNetConstant *makeNetConstant(const string *constant,
|
||||
int line);
|
||||
VerilogNetBitSelect *makeNetBitSelect(const string *name,
|
||||
int index);
|
||||
VerilogNetPartSelect *makeNetPartSelect(const string *name,
|
||||
int from_index,
|
||||
int to_index);
|
||||
VerilogModule *module(Cell *cell);
|
||||
Instance *linkNetwork(const char *top_cell_name,
|
||||
bool make_black_boxes);
|
||||
const char *filename() const { return filename_.c_str(); }
|
||||
void incrLine();
|
||||
Report *report() const { return report_; }
|
||||
void error(int id,
|
||||
const char *filename,
|
||||
int line,
|
||||
const char *fmt, ...);
|
||||
void warn(int id,
|
||||
const char *filename,
|
||||
int line,
|
||||
const char *fmt, ...);
|
||||
const string &zeroNetName() const { return zero_net_name_; }
|
||||
const string &oneNetName() const { return one_net_name_; }
|
||||
void deleteModules();
|
||||
void reportStmtCounts();
|
||||
const string &constant10Max() const { return constant10_max_; }
|
||||
|
||||
protected:
|
||||
void init(const char *filename);
|
||||
void makeCellPorts(Cell *cell,
|
||||
VerilogModule *module,
|
||||
VerilogNetSeq *ports);
|
||||
Port *makeCellPort(Cell *cell,
|
||||
VerilogModule *module,
|
||||
const string &port_name);
|
||||
void makeNamedPortRefCellPorts(Cell *cell,
|
||||
VerilogModule *module,
|
||||
VerilogNet *mod_port,
|
||||
StdStringSet &port_names);
|
||||
void checkModuleDcls(VerilogModule *module,
|
||||
set<string> &port_names);
|
||||
void makeModuleInstBody(VerilogModule *module,
|
||||
Instance *inst,
|
||||
VerilogBindingTbl *bindings,
|
||||
bool make_black_boxes);
|
||||
void makeModuleInstNetwork(VerilogModuleInst *mod_inst,
|
||||
Instance *parent,
|
||||
VerilogModule *parent_module,
|
||||
VerilogBindingTbl *parent_bindings,
|
||||
bool make_black_boxes);
|
||||
void makeLibertyInst(VerilogLibertyInst *lib_inst,
|
||||
Instance *parent,
|
||||
VerilogModule *parent_module,
|
||||
VerilogBindingTbl *parent_bindings);
|
||||
void bindGlobalNets(VerilogBindingTbl *bindings);
|
||||
void makeNamedInstPins1(Cell *cell,
|
||||
Instance *inst,
|
||||
VerilogModuleInst *mod_inst,
|
||||
VerilogBindingTbl *bindings,
|
||||
Instance *parent,
|
||||
VerilogBindingTbl *parent_bindings,
|
||||
bool is_leaf);
|
||||
void makeNamedInstPins(Cell *cell,
|
||||
Instance *inst,
|
||||
VerilogModuleInst *mod_inst,
|
||||
VerilogBindingTbl *bindings,
|
||||
Instance *parent,
|
||||
VerilogModule *parent_module,
|
||||
VerilogBindingTbl *parent_bindings,
|
||||
bool is_leaf);
|
||||
void makeOrderedInstPins(Cell *cell,
|
||||
Instance *inst,
|
||||
VerilogModuleInst *mod_inst,
|
||||
VerilogBindingTbl *bindings,
|
||||
Instance *parent,
|
||||
VerilogModule *parent_module,
|
||||
VerilogBindingTbl *parent_bindings,
|
||||
bool is_leaf);
|
||||
void mergeAssignNet(VerilogAssign *assign,
|
||||
VerilogModule *module,
|
||||
Instance *inst,
|
||||
VerilogBindingTbl *bindings);
|
||||
void makeInstPin(Instance *inst,
|
||||
Port *port,
|
||||
VerilogNetNameIterator *net_name_iter,
|
||||
VerilogBindingTbl *bindings,
|
||||
Instance *parent,
|
||||
VerilogBindingTbl *parent_bindings,
|
||||
bool is_leaf);
|
||||
void makeInstPin(Instance *inst,
|
||||
Port *port,
|
||||
const string &net_name,
|
||||
VerilogBindingTbl *bindings,
|
||||
Instance *parent,
|
||||
VerilogBindingTbl *parent_bindings,
|
||||
bool is_leaf);
|
||||
void linkWarn(int id,
|
||||
const char *filename,
|
||||
int line,
|
||||
const char *msg, ...)
|
||||
__attribute__((format (printf, 5, 6)));
|
||||
void linkError(int id,
|
||||
const char *filename,
|
||||
int line,
|
||||
const char *msg, ...)
|
||||
__attribute__((format (printf, 5, 6)));
|
||||
bool reportLinkErrors();
|
||||
bool haveLinkErrors();
|
||||
Cell *makeBlackBox(VerilogModuleInst *mod_inst,
|
||||
VerilogModule *parent_module);
|
||||
void makeBlackBoxNamedPorts(Cell *cell,
|
||||
VerilogModuleInst *mod_inst,
|
||||
VerilogModule *parent_module);
|
||||
void makeBlackBoxOrderedPorts(Cell *cell,
|
||||
VerilogModuleInst *mod_inst,
|
||||
VerilogModule *parent_module);
|
||||
bool isBlackBox(Cell *cell);
|
||||
bool hasScalarNamedPortRefs(LibertyCell *liberty_cell,
|
||||
VerilogNetSeq *pins);
|
||||
|
||||
string filename_;
|
||||
Report *report_;
|
||||
Debug *debug_;
|
||||
NetworkReader *network_;
|
||||
|
||||
Library *library_;
|
||||
int black_box_index_;
|
||||
VerilogModuleMap module_map_;
|
||||
VerilogErrorSeq link_errors_;
|
||||
const string zero_net_name_;
|
||||
const string one_net_name_;
|
||||
string constant10_max_;
|
||||
ViewType *view_type_;
|
||||
bool report_stmt_stats_;
|
||||
int module_count_;
|
||||
int inst_mod_count_;
|
||||
int inst_lib_count_;
|
||||
int inst_lib_net_arrays_;
|
||||
int port_names_;
|
||||
int inst_module_names_;
|
||||
int inst_names_;
|
||||
int dcl_count_;
|
||||
int dcl_bus_count_;
|
||||
int dcl_arg_count_;
|
||||
int net_scalar_count_;
|
||||
int net_scalar_names_;
|
||||
int net_bus_names_;
|
||||
int net_part_select_count_;
|
||||
int net_bit_select_count_;
|
||||
int net_port_ref_scalar_count_;
|
||||
int net_port_ref_scalar_net_count_;
|
||||
int net_port_ref_bit_count_;
|
||||
int net_port_ref_part_count_;
|
||||
int net_constant_count_;
|
||||
int assign_count_;
|
||||
int concat_count_;
|
||||
};
|
||||
|
||||
} // namespace sta
|
||||
|
||||
|
|
@ -16,314 +16,22 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#include "Zlib.hh"
|
||||
#include "Vector.hh"
|
||||
#include <string>
|
||||
|
||||
#include "Map.hh"
|
||||
#include "Vector.hh"
|
||||
#include "StringSeq.hh"
|
||||
#include "StringSet.hh"
|
||||
#include "NetworkClass.hh"
|
||||
|
||||
// Global namespace.
|
||||
#define YY_INPUT(buf,result,max_size) \
|
||||
sta::verilog_reader->getChars(buf, result, max_size)
|
||||
|
||||
int
|
||||
VerilogParse_error(const char *msg);
|
||||
|
||||
namespace sta {
|
||||
|
||||
using std::string;
|
||||
using std::vector;
|
||||
using std::set;
|
||||
|
||||
class Debug;
|
||||
class Report;
|
||||
class VerilogAttributeEntry;
|
||||
class VerilogAttributeStmt;
|
||||
class VerilogReader;
|
||||
class VerilogStmt;
|
||||
class VerilogNet;
|
||||
class VerilogNetScalar;
|
||||
class VerilogModule;
|
||||
class VerilogInst;
|
||||
class VerilogModuleInst;
|
||||
class VerilogLibertyInst;
|
||||
class VerilogDcl;
|
||||
class VerilogDclBus;
|
||||
class VerilogDclArg;
|
||||
class VerilogAssign;
|
||||
class VerilogNetConcat;
|
||||
class VerilogNetConstant;
|
||||
class VerilogNetBitSelect;
|
||||
class VerilogNetPartSelect;
|
||||
class StringRegistry;
|
||||
class VerilogBindingTbl;
|
||||
class VerilogNetNameIterator;
|
||||
class VerilogNetPortRef;
|
||||
class VerilogError;
|
||||
class LibertyCell;
|
||||
|
||||
typedef Vector<VerilogAttributeStmt*> VerilogAttributeStmtSeq;
|
||||
typedef Vector<VerilogAttributeEntry*> VerilogAttributeEntrySeq;
|
||||
typedef Vector<VerilogNet*> VerilogNetSeq;
|
||||
typedef Vector<VerilogStmt*> VerilogStmtSeq;
|
||||
typedef Map<const char*, VerilogDcl*, CharPtrLess> VerilogDclMap;
|
||||
typedef Vector<VerilogDclArg*> VerilogDclArgSeq;
|
||||
typedef Map<Cell*, VerilogModule*> VerilogModuleMap;
|
||||
typedef Vector<VerilogError*> VerilogErrorSeq;
|
||||
typedef Map<string, VerilogDcl*> VerilogDclMap;
|
||||
typedef Vector<bool> VerilogConstantValue;
|
||||
// Max base 10 constant net value (for strtoll).
|
||||
typedef unsigned long long VerilogConstant10;
|
||||
|
||||
extern VerilogReader *verilog_reader;
|
||||
|
||||
class VerilogReader
|
||||
{
|
||||
public:
|
||||
explicit VerilogReader(NetworkReader *network);
|
||||
~VerilogReader();
|
||||
bool read(const char *filename);
|
||||
// flex YY_INPUT yy_n_chars arg changed definition from int to size_t,
|
||||
// so provide both forms.
|
||||
void getChars(char *buf,
|
||||
size_t &result,
|
||||
size_t max_size);
|
||||
void getChars(char *buf,
|
||||
int &result,
|
||||
size_t max_size);
|
||||
void makeModule(const char *module_name,
|
||||
VerilogNetSeq *ports,
|
||||
VerilogStmtSeq *stmts,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
int line);
|
||||
void makeModule(const char *module_name,
|
||||
VerilogStmtSeq *port_dcls,
|
||||
VerilogStmtSeq *stmts,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
int line);
|
||||
VerilogDcl *makeDcl(PortDirection *dir,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line);
|
||||
VerilogDcl *makeDcl(PortDirection *dir,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line);
|
||||
VerilogDclArg *makeDclArg(const char *net_name);
|
||||
VerilogDclArg*makeDclArg(VerilogAssign *assign);
|
||||
VerilogDclBus *makeDclBus(PortDirection *dir,
|
||||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line);
|
||||
VerilogDclBus *makeDclBus(PortDirection *dir,
|
||||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line);
|
||||
VerilogInst *makeModuleInst(const char *module_name,
|
||||
const char *inst_name,
|
||||
VerilogNetSeq *pins,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
const int line);
|
||||
VerilogAssign *makeAssign(VerilogNet *lhs,
|
||||
VerilogNet *rhs,
|
||||
int line);
|
||||
VerilogNetScalar *makeNetScalar(const char *name);
|
||||
VerilogNetPortRef *makeNetNamedPortRefScalarNet(const char *port_vname);
|
||||
VerilogNetPortRef *makeNetNamedPortRefScalarNet(const char *port_name,
|
||||
const char *net_name);
|
||||
VerilogNetPortRef *makeNetNamedPortRefBitSelect(const char *port_name,
|
||||
const char *bus_name,
|
||||
int index);
|
||||
VerilogNetPortRef *makeNetNamedPortRefScalar(const char *port_name,
|
||||
VerilogNet *net);
|
||||
VerilogNetPortRef *makeNetNamedPortRefBit(const char *port_name,
|
||||
int index,
|
||||
VerilogNet *net);
|
||||
VerilogNetPortRef *makeNetNamedPortRefPart(const char *port_name,
|
||||
int from_index,
|
||||
int to_index,
|
||||
VerilogNet *net);
|
||||
VerilogNetConcat *makeNetConcat(VerilogNetSeq *nets);
|
||||
VerilogNetConstant *makeNetConstant(const char *constant);
|
||||
VerilogNetBitSelect *makeNetBitSelect(const char *name,
|
||||
int index);
|
||||
VerilogNetPartSelect *makeNetPartSelect(const char *name,
|
||||
int from_index,
|
||||
int to_index);
|
||||
VerilogModule *module(Cell *cell);
|
||||
Instance *linkNetwork(const char *top_cell_name,
|
||||
bool make_black_boxes,
|
||||
Report *report);
|
||||
int line() const { return line_; }
|
||||
const char *filename() const { return filename_.c_str(); }
|
||||
void incrLine();
|
||||
Report *report() const { return report_; }
|
||||
void error(int id,
|
||||
const char *filename,
|
||||
int line,
|
||||
const char *fmt, ...);
|
||||
void warn(int id,
|
||||
const char *filename,
|
||||
int line,
|
||||
const char *fmt, ...);
|
||||
const char *zeroNetName() const { return zero_net_name_; }
|
||||
const char *oneNetName() const { return one_net_name_; }
|
||||
void deleteModules();
|
||||
void reportStmtCounts();
|
||||
const char *constant10Max() const { return constant10_max_; }
|
||||
size_t constant10MaxLength() const { return constant10_max_length_; }
|
||||
string
|
||||
verilogName(VerilogModuleInst *inst);
|
||||
string
|
||||
instanceVerilogName(const char *inst_name);
|
||||
string
|
||||
netVerilogName(const char *net_name);
|
||||
static const char *unconnected_net_name_;
|
||||
|
||||
protected:
|
||||
void init(const char *filename);
|
||||
void makeCellPorts(Cell *cell,
|
||||
VerilogModule *module,
|
||||
VerilogNetSeq *ports);
|
||||
Port *makeCellPort(Cell *cell,
|
||||
VerilogModule *module,
|
||||
const char *port_name);
|
||||
void makeNamedPortRefCellPorts(Cell *cell,
|
||||
VerilogModule *module,
|
||||
VerilogNet *mod_port,
|
||||
set<string> &port_names);
|
||||
void checkModuleDcls(VerilogModule *module,
|
||||
set<string> &port_names);
|
||||
void makeModuleInstBody(VerilogModule *module,
|
||||
Instance *inst,
|
||||
VerilogBindingTbl *bindings,
|
||||
bool make_black_boxes);
|
||||
void makeModuleInstNetwork(VerilogModuleInst *mod_inst,
|
||||
Instance *parent,
|
||||
VerilogModule *parent_module,
|
||||
VerilogBindingTbl *parent_bindings,
|
||||
bool make_black_boxes);
|
||||
void makeLibertyInst(VerilogLibertyInst *lib_inst,
|
||||
Instance *parent,
|
||||
VerilogModule *parent_module,
|
||||
VerilogBindingTbl *parent_bindings);
|
||||
void bindGlobalNets(VerilogBindingTbl *bindings);
|
||||
void makeNamedInstPins1(Cell *cell,
|
||||
Instance *inst,
|
||||
VerilogModuleInst *mod_inst,
|
||||
VerilogBindingTbl *bindings,
|
||||
Instance *parent,
|
||||
VerilogBindingTbl *parent_bindings,
|
||||
bool is_leaf);
|
||||
void makeNamedInstPins(Cell *cell,
|
||||
Instance *inst,
|
||||
VerilogModuleInst *mod_inst,
|
||||
VerilogBindingTbl *bindings,
|
||||
Instance *parent,
|
||||
VerilogModule *parent_module,
|
||||
VerilogBindingTbl *parent_bindings,
|
||||
bool is_leaf);
|
||||
void makeOrderedInstPins(Cell *cell,
|
||||
Instance *inst,
|
||||
VerilogModuleInst *mod_inst,
|
||||
VerilogBindingTbl *bindings,
|
||||
Instance *parent,
|
||||
VerilogModule *parent_module,
|
||||
VerilogBindingTbl *parent_bindings,
|
||||
bool is_leaf);
|
||||
void mergeAssignNet(VerilogAssign *assign,
|
||||
VerilogModule *module,
|
||||
Instance *inst,
|
||||
VerilogBindingTbl *bindings);
|
||||
void makeInstPin(Instance *inst,
|
||||
Port *port,
|
||||
VerilogNetNameIterator *net_name_iter,
|
||||
VerilogBindingTbl *bindings,
|
||||
Instance *parent,
|
||||
VerilogBindingTbl *parent_bindings,
|
||||
bool is_leaf);
|
||||
void makeInstPin(Instance *inst,
|
||||
Port *port,
|
||||
const char *net_name,
|
||||
VerilogBindingTbl *bindings,
|
||||
Instance *parent,
|
||||
VerilogBindingTbl *parent_bindings,
|
||||
bool is_leaf);
|
||||
void linkWarn(int id,
|
||||
const char *filename,
|
||||
int line,
|
||||
const char *msg, ...)
|
||||
__attribute__((format (printf, 5, 6)));
|
||||
void linkError(int id,
|
||||
const char *filename,
|
||||
int line,
|
||||
const char *msg, ...)
|
||||
__attribute__((format (printf, 5, 6)));
|
||||
bool reportLinkErrors(Report *report);
|
||||
bool haveLinkErrors();
|
||||
Cell *makeBlackBox(VerilogModuleInst *mod_inst,
|
||||
VerilogModule *parent_module);
|
||||
void makeBlackBoxNamedPorts(Cell *cell,
|
||||
VerilogModuleInst *mod_inst,
|
||||
VerilogModule *parent_module);
|
||||
void makeBlackBoxOrderedPorts(Cell *cell,
|
||||
VerilogModuleInst *mod_inst,
|
||||
VerilogModule *parent_module);
|
||||
bool isBlackBox(Cell *cell);
|
||||
bool hasScalarNamedPortRefs(LibertyCell *liberty_cell,
|
||||
VerilogNetSeq *pins);
|
||||
|
||||
Report *report_;
|
||||
Debug *debug_;
|
||||
NetworkReader *network_;
|
||||
|
||||
string filename_;
|
||||
vector<string> filenames_;
|
||||
int line_;
|
||||
gzFile stream_;
|
||||
|
||||
Library *library_;
|
||||
int black_box_index_;
|
||||
VerilogModuleMap module_map_;
|
||||
VerilogErrorSeq link_errors_;
|
||||
const char *zero_net_name_;
|
||||
const char *one_net_name_;
|
||||
const char *constant10_max_;
|
||||
size_t constant10_max_length_;
|
||||
ViewType *view_type_;
|
||||
bool report_stmt_stats_;
|
||||
int module_count_;
|
||||
int inst_mod_count_;
|
||||
int inst_lib_count_;
|
||||
int inst_lib_net_arrays_;
|
||||
int port_names_;
|
||||
int inst_module_names_;
|
||||
int inst_names_;
|
||||
int dcl_count_;
|
||||
int dcl_bus_count_;
|
||||
int dcl_arg_count_;
|
||||
int net_scalar_count_;
|
||||
int net_scalar_names_;
|
||||
int net_bus_names_;
|
||||
int net_part_select_count_;
|
||||
int net_bit_select_count_;
|
||||
int net_port_ref_scalar_count_;
|
||||
int net_port_ref_scalar_net_count_;
|
||||
int net_port_ref_bit_count_;
|
||||
int net_port_ref_part_count_;
|
||||
int net_constant_count_;
|
||||
int assign_count_;
|
||||
int concat_count_;
|
||||
};
|
||||
typedef vector<string> StdStringSeq;
|
||||
|
||||
class VerilogStmt
|
||||
{
|
||||
public:
|
||||
explicit VerilogStmt(int line);
|
||||
VerilogStmt(int line);
|
||||
virtual ~VerilogStmt() {}
|
||||
virtual bool isInstance() const { return false; }
|
||||
virtual bool isModuleInst() const { return false; }
|
||||
|
|
@ -339,19 +47,19 @@ private:
|
|||
class VerilogModule : public VerilogStmt
|
||||
{
|
||||
public:
|
||||
VerilogModule(const char *name,
|
||||
VerilogModule(const string &name,
|
||||
VerilogNetSeq *ports,
|
||||
VerilogStmtSeq *stmts,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
string &filename,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
const string &filename,
|
||||
int line,
|
||||
VerilogReader *reader);
|
||||
virtual ~VerilogModule();
|
||||
const char *name() { return name_; }
|
||||
const string &name() { return name_; }
|
||||
const char *filename() { return filename_.c_str(); }
|
||||
VerilogAttributeStmtSeq *attributeStmts() { return attribute_stmts_; }
|
||||
VerilogAttrStmtSeq *attrStmts() { return attr_stmts_; }
|
||||
VerilogNetSeq *ports() { return ports_; }
|
||||
VerilogDcl *declaration(const char *net_name);
|
||||
VerilogDcl *declaration(const string &net_name);
|
||||
VerilogStmtSeq *stmts() { return stmts_; }
|
||||
VerilogDclMap *declarationMap() { return &dcl_map_; }
|
||||
void parseDcl(VerilogDcl *dcl,
|
||||
|
|
@ -360,15 +68,15 @@ public:
|
|||
private:
|
||||
void parseStmts(VerilogReader *reader);
|
||||
void checkInstanceName(VerilogInst *inst,
|
||||
StringSet &inst_names,
|
||||
StdStringSet &inst_names,
|
||||
VerilogReader *reader);
|
||||
|
||||
const char *name_;
|
||||
string &filename_;
|
||||
string name_;
|
||||
string filename_;
|
||||
VerilogNetSeq *ports_;
|
||||
VerilogStmtSeq *stmts_;
|
||||
VerilogDclMap dcl_map_;
|
||||
VerilogAttributeStmtSeq *attribute_stmts_;
|
||||
VerilogAttrStmtSeq *attr_stmts_;
|
||||
};
|
||||
|
||||
class VerilogDcl : public VerilogStmt
|
||||
|
|
@ -376,14 +84,14 @@ class VerilogDcl : public VerilogStmt
|
|||
public:
|
||||
VerilogDcl(PortDirection *dir,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
int line);
|
||||
VerilogDcl(PortDirection *dir,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
int line);
|
||||
virtual ~VerilogDcl();
|
||||
const char *portName();
|
||||
const string &portName();
|
||||
virtual bool isBus() const { return false; }
|
||||
virtual bool isDeclaration() const { return true; }
|
||||
VerilogDclArgSeq *args() const { return args_; }
|
||||
|
|
@ -395,7 +103,7 @@ public:
|
|||
private:
|
||||
PortDirection *dir_;
|
||||
VerilogDclArgSeq *args_;
|
||||
VerilogAttributeStmtSeq *attribute_stmts_;
|
||||
VerilogAttrStmtSeq *attr_stmts_;
|
||||
};
|
||||
|
||||
class VerilogDclBus : public VerilogDcl
|
||||
|
|
@ -405,13 +113,13 @@ public:
|
|||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
int line);
|
||||
VerilogDclBus(PortDirection *dir,
|
||||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
int line);
|
||||
virtual bool isBus() const { return true; }
|
||||
int fromIndex() const { return from_index_; }
|
||||
|
|
@ -427,14 +135,15 @@ private:
|
|||
class VerilogDclArg
|
||||
{
|
||||
public:
|
||||
explicit VerilogDclArg(const char *net_name);
|
||||
explicit VerilogDclArg(VerilogAssign *assign);
|
||||
VerilogDclArg(const string &net_name);
|
||||
VerilogDclArg(VerilogAssign *assign);
|
||||
~VerilogDclArg();
|
||||
const char *netName();
|
||||
const string &netName();
|
||||
bool isNamed() const { return assign_ == nullptr; }
|
||||
VerilogAssign *assign() { return assign_; }
|
||||
|
||||
private:
|
||||
const char *net_name_;
|
||||
string net_name_;
|
||||
VerilogAssign *assign_;
|
||||
};
|
||||
|
||||
|
|
@ -458,37 +167,37 @@ private:
|
|||
class VerilogInst : public VerilogStmt
|
||||
{
|
||||
public:
|
||||
VerilogInst(const char *inst_name,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
VerilogInst(const string &inst_name,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
const int line);
|
||||
virtual ~VerilogInst();
|
||||
virtual bool isInstance() const { return true; }
|
||||
const char *instanceName() const { return inst_name_; }
|
||||
VerilogAttributeStmtSeq *attributeStmts() const { return attribute_stmts_; }
|
||||
void setInstanceName(const char *inst_name);
|
||||
const string &instanceName() const { return inst_name_; }
|
||||
VerilogAttrStmtSeq *attrStmts() const { return attr_stmts_; }
|
||||
void setInstanceName(const string &inst_name);
|
||||
|
||||
private:
|
||||
const char *inst_name_;
|
||||
VerilogAttributeStmtSeq* attribute_stmts_;
|
||||
string inst_name_;
|
||||
VerilogAttrStmtSeq *attr_stmts_;
|
||||
};
|
||||
|
||||
class VerilogModuleInst : public VerilogInst
|
||||
{
|
||||
public:
|
||||
VerilogModuleInst(const char *module_name,
|
||||
const char *inst_name,
|
||||
VerilogModuleInst(const string &module_name,
|
||||
const string &inst_name,
|
||||
VerilogNetSeq *pins,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
const int line);
|
||||
virtual ~VerilogModuleInst();
|
||||
virtual bool isModuleInst() const { return true; }
|
||||
const char *moduleName() const { return module_name_; }
|
||||
const string &moduleName() const { return module_name_; }
|
||||
VerilogNetSeq *pins() const { return pins_; }
|
||||
bool namedPins();
|
||||
bool hasPins();
|
||||
|
||||
private:
|
||||
const char *module_name_;
|
||||
string module_name_;
|
||||
VerilogNetSeq *pins_;
|
||||
};
|
||||
|
||||
|
|
@ -499,18 +208,17 @@ class VerilogLibertyInst : public VerilogInst
|
|||
{
|
||||
public:
|
||||
VerilogLibertyInst(LibertyCell *cell,
|
||||
const char *inst_name,
|
||||
const char **net_names,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
const string &inst_name,
|
||||
const StdStringSeq &net_names,
|
||||
VerilogAttrStmtSeq *attr_stmts,
|
||||
const int line);
|
||||
virtual ~VerilogLibertyInst();
|
||||
virtual bool isLibertyInst() const { return true; }
|
||||
LibertyCell *cell() const { return cell_; }
|
||||
const char **netNames() const { return net_names_; }
|
||||
const StdStringSeq &netNames() const { return net_names_; }
|
||||
|
||||
private:
|
||||
LibertyCell *cell_;
|
||||
const char **net_names_;
|
||||
StdStringSeq net_names_;
|
||||
};
|
||||
|
||||
// Abstract base class for nets.
|
||||
|
|
@ -526,8 +234,6 @@ public:
|
|||
virtual int size(VerilogModule *module) = 0;
|
||||
virtual VerilogNetNameIterator *nameIterator(VerilogModule *module,
|
||||
VerilogReader *reader) = 0;
|
||||
|
||||
private:
|
||||
};
|
||||
|
||||
class VerilogNetUnnamed : public VerilogNet
|
||||
|
|
@ -544,14 +250,11 @@ private:
|
|||
class VerilogNetNamed : public VerilogNet
|
||||
{
|
||||
public:
|
||||
explicit VerilogNetNamed(const char *name);
|
||||
explicit VerilogNetNamed(const string &name);
|
||||
VerilogNetNamed(const string &name);
|
||||
virtual ~VerilogNetNamed();
|
||||
bool isNamed() const override { return true; }
|
||||
virtual bool isScalar() const = 0;
|
||||
const string &name() const override { return name_; }
|
||||
const string baseName() const { return name_; }
|
||||
void setName(const char *name);
|
||||
|
||||
protected:
|
||||
string name_;
|
||||
|
|
@ -561,7 +264,7 @@ protected:
|
|||
class VerilogNetScalar : public VerilogNetNamed
|
||||
{
|
||||
public:
|
||||
explicit VerilogNetScalar(const char *name);
|
||||
VerilogNetScalar(const string &name);
|
||||
virtual bool isScalar() const { return true; }
|
||||
virtual int size(VerilogModule *module);
|
||||
virtual VerilogNetNameIterator *nameIterator(VerilogModule *module,
|
||||
|
|
@ -571,7 +274,7 @@ public:
|
|||
class VerilogNetBitSelect : public VerilogNetNamed
|
||||
{
|
||||
public:
|
||||
VerilogNetBitSelect(const char *name,
|
||||
VerilogNetBitSelect(const string &name,
|
||||
int index);
|
||||
int index() { return index_; }
|
||||
virtual bool isScalar() const { return false; }
|
||||
|
|
@ -585,7 +288,7 @@ private:
|
|||
class VerilogNetPartSelect : public VerilogNetNamed
|
||||
{
|
||||
public:
|
||||
VerilogNetPartSelect(const char *name,
|
||||
VerilogNetPartSelect(const string &name,
|
||||
int from_index,
|
||||
int to_index);
|
||||
virtual bool isScalar() const { return false; }
|
||||
|
|
@ -603,24 +306,26 @@ private:
|
|||
class VerilogNetConstant : public VerilogNetUnnamed
|
||||
{
|
||||
public:
|
||||
VerilogNetConstant(const char *constant,
|
||||
VerilogReader *reader);
|
||||
VerilogNetConstant(const string *constant,
|
||||
VerilogReader *reader,
|
||||
int line);
|
||||
virtual ~VerilogNetConstant();
|
||||
virtual int size(VerilogModule *module);
|
||||
virtual VerilogNetNameIterator *nameIterator(VerilogModule *module,
|
||||
VerilogReader *reader);
|
||||
|
||||
private:
|
||||
void parseConstant(const char *constant,
|
||||
VerilogReader *reader);
|
||||
void parseConstant(const char *constant,
|
||||
size_t constant_length,
|
||||
const char *base_ptr,
|
||||
void parseConstant(const string *constant,
|
||||
VerilogReader *reader,
|
||||
int line);
|
||||
void parseConstant(const string *constant,
|
||||
size_t base_idx,
|
||||
int base,
|
||||
int digit_bit_count);
|
||||
void parseConstant10(const char *constant_str,
|
||||
char *tmp,
|
||||
VerilogReader *reader);
|
||||
void parseConstant10(const string *constant,
|
||||
size_t base_idx,
|
||||
VerilogReader *reader,
|
||||
int line);
|
||||
|
||||
VerilogConstantValue *value_;
|
||||
};
|
||||
|
|
@ -628,7 +333,7 @@ private:
|
|||
class VerilogNetConcat : public VerilogNetUnnamed
|
||||
{
|
||||
public:
|
||||
explicit VerilogNetConcat(VerilogNetSeq *nets);
|
||||
VerilogNetConcat(VerilogNetSeq *nets);
|
||||
virtual ~VerilogNetConcat();
|
||||
virtual int size(VerilogModule *module);
|
||||
virtual VerilogNetNameIterator *nameIterator(VerilogModule *module,
|
||||
|
|
@ -642,7 +347,7 @@ private:
|
|||
class VerilogNetPortRef : public VerilogNetScalar
|
||||
{
|
||||
public:
|
||||
explicit VerilogNetPortRef(const char *name);
|
||||
VerilogNetPortRef(const string &name);
|
||||
virtual bool isNamedPortRef() { return true; }
|
||||
virtual bool hasNet() = 0;
|
||||
};
|
||||
|
|
@ -654,27 +359,26 @@ public:
|
|||
class VerilogNetPortRefScalarNet : public VerilogNetPortRef
|
||||
{
|
||||
public:
|
||||
VerilogNetPortRefScalarNet(const char *name);
|
||||
VerilogNetPortRefScalarNet(const char *name,
|
||||
const char *net_name);
|
||||
virtual ~VerilogNetPortRefScalarNet();
|
||||
VerilogNetPortRefScalarNet(const string &name);
|
||||
VerilogNetPortRefScalarNet(const string &name,
|
||||
const string &net_name);
|
||||
virtual bool isScalar() const { return true; }
|
||||
virtual bool isNamedPortRefScalarNet() const { return true; }
|
||||
virtual int size(VerilogModule *module);
|
||||
virtual VerilogNetNameIterator *nameIterator(VerilogModule *module,
|
||||
VerilogReader *reader);
|
||||
virtual bool hasNet() { return net_name_ != nullptr; }
|
||||
const char *netName() const { return net_name_; }
|
||||
void setNetName(const char *net_name) { net_name_ = net_name; }
|
||||
virtual bool hasNet() { return !net_name_.empty(); }
|
||||
const string &netName() const { return net_name_; }
|
||||
void setNetName(const string &net_name) { net_name_ = net_name; }
|
||||
|
||||
private:
|
||||
const char *net_name_;
|
||||
string net_name_;
|
||||
};
|
||||
|
||||
class VerilogNetPortRefScalar : public VerilogNetPortRef
|
||||
{
|
||||
public:
|
||||
VerilogNetPortRefScalar(const char *name,
|
||||
VerilogNetPortRefScalar(const string &name,
|
||||
VerilogNet *net);
|
||||
virtual ~VerilogNetPortRefScalar();
|
||||
virtual bool isScalar() const { return true; }
|
||||
|
|
@ -690,7 +394,7 @@ private:
|
|||
class VerilogNetPortRefBit : public VerilogNetPortRefScalar
|
||||
{
|
||||
public:
|
||||
VerilogNetPortRefBit(const char *name,
|
||||
VerilogNetPortRefBit(const string &name,
|
||||
int index,
|
||||
VerilogNet *net);
|
||||
const string &name() const override { return bit_name_; }
|
||||
|
|
@ -702,7 +406,7 @@ private:
|
|||
class VerilogNetPortRefPart : public VerilogNetPortRefBit
|
||||
{
|
||||
public:
|
||||
VerilogNetPortRefPart(const char *name,
|
||||
VerilogNetPortRefPart(const string &name,
|
||||
int from_index,
|
||||
int to_index,
|
||||
VerilogNet *net);
|
||||
|
|
@ -714,33 +418,33 @@ private:
|
|||
};
|
||||
|
||||
// Abstract class for iterating over the component nets of a net.
|
||||
class VerilogNetNameIterator : public Iterator<const char*>
|
||||
class VerilogNetNameIterator : public Iterator<const string&>
|
||||
{
|
||||
};
|
||||
|
||||
class VerilogAttributeStmt
|
||||
class VerilogAttrStmt
|
||||
{
|
||||
public:
|
||||
VerilogAttributeStmt(VerilogAttributeEntrySeq *attribute_sequence);
|
||||
VerilogAttributeEntrySeq *attribute_sequence();
|
||||
virtual ~VerilogAttributeStmt();
|
||||
VerilogAttrStmt(VerilogAttrEntrySeq *attrs);
|
||||
VerilogAttrEntrySeq *attrs();
|
||||
virtual ~VerilogAttrStmt();
|
||||
|
||||
private:
|
||||
VerilogAttributeEntrySeq *attribute_sequence_;
|
||||
VerilogAttrEntrySeq *attrs_;
|
||||
};
|
||||
|
||||
class VerilogAttributeEntry
|
||||
class VerilogAttrEntry
|
||||
{
|
||||
public:
|
||||
VerilogAttributeEntry(std::string key,
|
||||
std::string value);
|
||||
virtual std::string key();
|
||||
virtual std::string value();
|
||||
virtual ~VerilogAttributeEntry() = default;
|
||||
VerilogAttrEntry(const string &key,
|
||||
const string &value);
|
||||
virtual string key();
|
||||
virtual string value();
|
||||
virtual ~VerilogAttrEntry() = default;
|
||||
|
||||
private:
|
||||
std::string key_;
|
||||
std::string value_;
|
||||
string key_;
|
||||
string value_;
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
|
|
|||
|
|
@ -16,17 +16,38 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#ifndef __FLEX_LEXER_H
|
||||
#include <FlexLexer.h>
|
||||
#endif
|
||||
|
||||
#include "location.hh"
|
||||
#include "VerilogParse.hh"
|
||||
|
||||
namespace sta {
|
||||
|
||||
class NetworkReader;
|
||||
class Report;
|
||||
|
||||
// Return true if successful.
|
||||
bool
|
||||
readVerilogFile(const char *filename,
|
||||
NetworkReader *network);
|
||||
class VerilogScanner : public yyFlexLexer
|
||||
{
|
||||
public:
|
||||
VerilogScanner(std::istream *stream,
|
||||
const char *filename,
|
||||
Report *report);
|
||||
virtual ~VerilogScanner() {}
|
||||
|
||||
void
|
||||
deleteVerilogReader();
|
||||
virtual int yylex(VerilogParse::semantic_type *const yylval,
|
||||
VerilogParse::location_type *yylloc);
|
||||
// YY_DECL defined in VerilogLex.ll
|
||||
// Method body created by flex in VerilogLex.yy.cc
|
||||
|
||||
} // namespace sta
|
||||
void error(const char *msg);
|
||||
|
||||
// Get rid of override virtual function warning.
|
||||
using FlexLexer::yylex;
|
||||
|
||||
private:
|
||||
const char *filename_;
|
||||
Report *report_;
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
|
@ -194,9 +194,8 @@ VerilogWriter::writePorts(const Cell *cell)
|
|||
|| !network_->direction(port)->isPowerGround()) {
|
||||
if (!first)
|
||||
fprintf(stream_, ",\n ");
|
||||
string verillg_name = portVerilogName(network_->name(port),
|
||||
network_->pathEscape());
|
||||
fprintf(stream_, "%s", verillg_name.c_str());
|
||||
string verilog_name = portVerilogName(network_->name(port));
|
||||
fprintf(stream_, "%s", verilog_name.c_str());
|
||||
first = false;
|
||||
}
|
||||
}
|
||||
|
|
@ -213,8 +212,7 @@ VerilogWriter::writePortDcls(const Cell *cell)
|
|||
PortDirection *dir = network_->direction(port);
|
||||
if (include_pwr_gnd_
|
||||
|| !network_->direction(port)->isPowerGround()) {
|
||||
string port_vname = portVerilogName(network_->name(port),
|
||||
network_->pathEscape());
|
||||
string port_vname = portVerilogName(network_->name(port));
|
||||
const char *vtype = verilogPortDir(dir);
|
||||
if (vtype) {
|
||||
fprintf(stream_, " %s", vtype);
|
||||
|
|
@ -252,8 +250,9 @@ VerilogWriter::verilogPortDir(PortDirection *dir)
|
|||
return "inout";
|
||||
else if (dir == PortDirection::ground())
|
||||
return "inout";
|
||||
else if (dir == PortDirection::internal())
|
||||
return nullptr;
|
||||
else if (dir == PortDirection::internal()
|
||||
|| dir == PortDirection::unknown())
|
||||
return "inout";
|
||||
else {
|
||||
criticalError(268, "unknown port direction");
|
||||
return nullptr;
|
||||
|
|
@ -285,7 +284,7 @@ VerilogWriter::writeWireDcls(const Instance *inst)
|
|||
range.second = min(range.second, index);
|
||||
}
|
||||
else {
|
||||
string net_vname = netVerilogName(net_name, network_->pathEscape());
|
||||
string net_vname = netVerilogName(net_name);
|
||||
fprintf(stream_, " wire %s;\n", net_vname.c_str());;
|
||||
}
|
||||
}
|
||||
|
|
@ -295,7 +294,7 @@ VerilogWriter::writeWireDcls(const Instance *inst)
|
|||
|
||||
for (const auto& [bus_name1, range] : bus_ranges) {
|
||||
const char *bus_name = bus_name1.c_str();
|
||||
string net_vname = netVerilogName(bus_name, network_->pathEscape());
|
||||
string net_vname = netVerilogName(bus_name);
|
||||
fprintf(stream_, " wire [%d:%d] %s;\n",
|
||||
range.first,
|
||||
range.second,
|
||||
|
|
@ -335,7 +334,7 @@ VerilogWriter::writeChild(const Instance *child)
|
|||
Cell *child_cell = network_->cell(child);
|
||||
if (!remove_cells_.hasKey(child_cell)) {
|
||||
const char *child_name = network_->name(child);
|
||||
string child_vname = instanceVerilogName(child_name, network_->pathEscape());
|
||||
string child_vname = instanceVerilogName(child_name);
|
||||
string child_cell_vname = cellVerilogName(network_->name(child_cell));
|
||||
fprintf(stream_, " %s %s (",
|
||||
child_cell_vname.c_str(),
|
||||
|
|
@ -367,11 +366,10 @@ VerilogWriter::writeInstPin(const Instance *inst,
|
|||
Net *net = network_->net(pin);
|
||||
if (net) {
|
||||
const char *net_name = network_->name(net);
|
||||
string net_vname = netVerilogName(net_name, network_->pathEscape());
|
||||
string net_vname = netVerilogName(net_name);
|
||||
if (!first_port)
|
||||
fprintf(stream_, ",\n ");
|
||||
string port_vname = portVerilogName(network_->name(port),
|
||||
network_->pathEscape());
|
||||
string port_vname = portVerilogName(network_->name(port));
|
||||
fprintf(stream_, ".%s(%s)",
|
||||
port_vname.c_str(),
|
||||
net_vname.c_str());
|
||||
|
|
@ -427,7 +425,7 @@ VerilogWriter::writeInstBusPinBit(const Instance *inst,
|
|||
else
|
||||
// There is no verilog syntax to "skip" a bit in the concatentation.
|
||||
stringPrint(net_name, "_NC%d", unconnected_net_index_++);
|
||||
string net_vname = netVerilogName(net_name.c_str(), network_->pathEscape());
|
||||
string net_vname = netVerilogName(net_name.c_str());
|
||||
if (!first_member)
|
||||
fprintf(stream_, ",\n ");
|
||||
fprintf(stream_, "%s", net_vname.c_str());
|
||||
|
|
@ -454,10 +452,8 @@ VerilogWriter::writeAssigns(const Instance *inst)
|
|||
|| (include_pwr_gnd_ && network_->direction(port)->isPowerGround()))
|
||||
&& !stringEqual(network_->name(port), network_->name(net))) {
|
||||
// Port name is different from net name.
|
||||
string port_vname = netVerilogName(network_->name(port),
|
||||
network_->pathEscape());
|
||||
string net_vname = netVerilogName(network_->name(net),
|
||||
network_->pathEscape());
|
||||
string port_vname = netVerilogName(network_->name(port));
|
||||
string net_vname = netVerilogName(network_->name(net));
|
||||
fprintf(stream_, " assign %s = %s;\n",
|
||||
port_vname.c_str(),
|
||||
net_vname.c_str());
|
||||
|
|
|
|||
Loading…
Reference in New Issue