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OpenSTA/verilog/test
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Jaehyun Kim 547737f71e test: Apply review feedback - part2 
- Remove stale line-number coverage comments (# Targets: line NNN, hit=0)
- Remove useless file-existence checks from verilog/sdf tests
- Delete 21 orphaned dcalc Tcl tests (C++ tests already cover them)
- Rename liberty_ccsn_ecsm -> liberty_ccsn (no ECSM libs available)
- Fix liberty_sky130_corners to use define_corners/-corner for real multi-corner testing
- Add report_checks per wireload model in liberty_wireload
- Fix test/regression to work from test/ directory (label mismatch)
- Refactor all module CMakeLists.txt with sta_module_tests() macro

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
 		2026-02-20 01:13:42 +09:00
..
cpp test: Refactoring. Standardize Google Test naming conventions by removing `R#_` prefixes, improve temporary file creation with `mkstemp`, etc 2026-02-13 20:36:42 +09:00
CMakeLists.txt test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
assign_net.v test: Initial upload 2026-02-13 19:19:09 +09:00
bus_connect.v test: Initial upload 2026-02-13 19:19:09 +09:00
constant_net.v test: Initial upload 2026-02-13 19:19:09 +09:00
positional.v test: Initial upload 2026-02-13 19:19:09 +09:00
regression test: Initial upload 2026-02-13 19:19:09 +09:00
verilog_assign.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_assign.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_assign_test.v test: Initial upload 2026-02-13 19:19:09 +09:00
verilog_attributes.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_attributes.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_bus.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_bus.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_bus_partselect.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_bus_partselect.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_bus_partselect.v test: Initial upload 2026-02-13 19:19:09 +09:00
verilog_bus_test.v test: Initial upload 2026-02-13 19:19:09 +09:00
verilog_complex_bus.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_complex_bus.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_complex_bus_test.v test: Initial upload 2026-02-13 19:19:09 +09:00
verilog_const_concat.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_const_concat.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_const_concat.v test: Initial upload 2026-02-13 19:19:09 +09:00
verilog_coverage.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_coverage.tcl test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_coverage_test.v test: Initial upload 2026-02-13 19:19:09 +09:00
verilog_error_paths.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_error_paths.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_error_paths.v test: Initial upload 2026-02-13 19:19:09 +09:00
verilog_escaped_write.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_escaped_write.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_gcd_large.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_gcd_large.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_gcd_writer.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_gcd_writer.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_hier_write.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_hier_write.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_multimodule_write.ok test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_multimodule_write.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_preproc_param.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_preproc_param.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_preproc_param.v test: Initial upload 2026-02-13 19:19:09 +09:00
verilog_read_asap7.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_read_asap7.tcl test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_remove_cells.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_remove_cells.tcl test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_roundtrip.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_roundtrip.tcl test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_roundtrip.vok test: Initial upload 2026-02-13 19:19:09 +09:00
verilog_specify.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_specify.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_supply_tristate.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_supply_tristate.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_supply_tristate.v test: Initial upload 2026-02-13 19:19:09 +09:00
verilog_test1.v test: Initial upload 2026-02-13 19:19:09 +09:00
verilog_write_asap7.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_asap7.tcl test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_assign_types.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_assign_types.tcl test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_bus_types.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_bus_types.tcl test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_complex_bus_types.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_complex_bus_types.tcl test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_nangate.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_nangate.tcl test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_nangate_out1.vok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_nangate_out2.vok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_options.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_options.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
verilog_write_sky130.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_write_sky130.tcl test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_writer_advanced.ok test: Apply review feedback - part1 2026-02-19 23:30:23 +09:00
verilog_writer_advanced.tcl test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00