131 lines
4.5 KiB
Tcl
131 lines
4.5 KiB
Tcl
# Test VerilogReader and VerilogWriter with multiple design reads,
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# link re-entries, writing with all options, and diverse verilog constructs.
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# Targets:
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# VerilogReader.cc: readVerilog (multiple reads), clearNetwork,
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# makeModule (re-define), makeModuleInst, makeDcl, makeDclArg,
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# linkNetwork (re-link), checkModule, resolveModule
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# VerilogWriter.cc: writeVerilog (all option combinations),
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# writePowerGround, writeSort, -no_port_dir
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source ../../test/helpers.tcl
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############################################################
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# Test 1: Read and write Nangate example designs
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############################################################
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puts "--- Test 1: Nangate examples ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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# Read example1.v
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read_verilog ../../examples/example1.v
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link_design top
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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# Write in several styles
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set out1 [make_result_file verilog_mm_default.v]
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write_verilog $out1
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set out2 [make_result_file verilog_mm_pwr.v]
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write_verilog -include_pwr_gnd $out2
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set out3 [make_result_file verilog_mm_sort.v]
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write_verilog -sort $out3
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set out4 [make_result_file verilog_mm_pwr_sort.v]
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write_verilog -include_pwr_gnd -sort $out4
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############################################################
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# Test 2: Re-read written verilog
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############################################################
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puts "--- Test 2: re-read default ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out1
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link_design top
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puts "re-read cells: [llength [get_cells *]]"
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############################################################
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# Test 3: Re-read power/ground version
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############################################################
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puts "--- Test 3: re-read pwr ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out2
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link_design top
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puts "re-read pwr cells: [llength [get_cells *]]"
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############################################################
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# Test 4: Timing after re-read
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############################################################
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puts "--- Test 4: timing after re-read ---"
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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set_output_delay -clock clk 0 [get_ports out]
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set_input_transition 0.1 [all_inputs]
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report_checks
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report_checks -path_delay min
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report_checks -fields {slew cap input_pins nets fanout}
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############################################################
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# Test 5: Instance/net queries
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############################################################
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puts "--- Test 5: queries ---"
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foreach inst_name {r1 r2 r3 u1 u2} {
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set inst [get_cells $inst_name]
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set ref [get_property $inst ref_name]
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puts "$inst_name ref=$ref"
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}
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foreach net_name {r1q r2q u1z u2z} {
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report_net $net_name
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}
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############################################################
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# Test 6: Write and re-read the sorted version
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############################################################
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puts "--- Test 6: sorted re-read ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out3
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link_design top
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puts "sorted cells: [llength [get_cells *]]"
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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report_checks
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############################################################
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# Test 7: Read reg1_asap7 design
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############################################################
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puts "--- Test 7: ASAP7 design ---"
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read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
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read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
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read_verilog ../../test/reg1_asap7.v
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link_design top
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set out5 [make_result_file verilog_mm_asap7.v]
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write_verilog $out5
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set out6 [make_result_file verilog_mm_asap7_pwr.v]
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write_verilog -include_pwr_gnd $out6
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# Re-read ASAP7 written verilog
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read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
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read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
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read_verilog $out5
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link_design top
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puts "re-read ASAP7 cells: [llength [get_cells *]]"
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create_clock -name clk -period 500 {clk1 clk2 clk3}
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set_input_delay -clock clk 1 {in1 in2}
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set_output_delay -clock clk 1 [get_ports out]
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report_checks
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