OpenSTA/verilog
Jaehyun Kim 547737f71e test: Apply review feedback - part2
- Remove stale line-number coverage comments (# Targets: line NNN, hit=0)
- Remove useless file-existence checks from verilog/sdf tests
- Delete 21 orphaned dcalc Tcl tests (C++ tests already cover them)
- Rename liberty_ccsn_ecsm -> liberty_ccsn (no ECSM libs available)
- Fix liberty_sky130_corners to use define_corners/-corner for real multi-corner testing
- Add report_checks per wireload model in liberty_wireload
- Fix test/regression to work from test/ directory (label mismatch)
- Refactor all module CMakeLists.txt with sta_module_tests() macro

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-02-20 01:13:42 +09:00
..
test test: Apply review feedback - part2 2026-02-20 01:13:42 +09:00
Verilog.i rm write_verilog -sort 2025-12-12 09:40:45 -07:00
Verilog.tcl rm write_verilog -sort 2025-12-12 09:40:45 -07:00
VerilogLex.ll Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogParse.yy Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogReader.cc Fix C++20 warning (#337) 2025-11-21 07:02:35 -08:00
VerilogReader.hh remove using std from headers 2025-04-11 16:59:48 -07:00
VerilogReaderPvt.hh remove using std from headers 2025-04-11 16:59:48 -07:00
VerilogScanner.hh LibExpr/spef/saif c++ parsers 2025-02-01 14:49:30 -08:00
VerilogWriter.cc rm write_verilog -sort 2025-12-12 09:40:45 -07:00