OpenSTA/verilog/test/CMakeLists.txt

33 lines
515 B
CMake

sta_module_tests("verilog"
TESTS
assign
attributes
bus
bus_partselect
complex_bus
const_concat
coverage
error_paths
escaped_write
gcd_large
gcd_writer
hier_write
multimodule_write
preproc_param
read_asap7
remove_cells
roundtrip
specify
supply_tristate
write_asap7
write_assign_types
write_bus_types
write_complex_bus_types
write_nangate
write_options
write_sky130
writer_advanced
)
add_subdirectory(cpp)