James Cherry
|
7fdeb0d3b7
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use range iter
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2020-02-01 18:13:41 -07:00 |
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James Cherry
|
26c76cd075
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verilog reader make instances with liberty cell
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2020-02-01 10:55:27 -07:00 |
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James Cherry
|
74e287a7eb
|
write_verilog escaped bus port name "input [7:0] \in[0] ;"
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2019-07-03 21:18:38 -07:00 |
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James Cherry
|
eb9fdd1be0
|
write verilog match liberty bus bit order
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2019-07-02 07:07:34 -07:00 |
|
James Cherry
|
344394de29
|
link_design use verilog library to lookup top
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2019-06-26 16:01:58 -07:00 |
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James Cherry
|
1a84830895
|
sta::worst_slack args, sta to verilog name args
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2019-06-18 15:52:12 -07:00 |
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James Cherry
|
49b2c3cea7
|
rm redundant StaState args
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2019-06-17 08:32:28 -07:00 |
|
James Cherry
|
96fcf1d8b2
|
ConcreteCell/Port pointers to corresponding liberty
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2019-06-15 22:20:54 -07:00 |
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James Cherry
|
a988588dac
|
sync
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2019-05-19 17:06:06 -06:00 |
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James Cherry
|
2d519b4740
|
ucsd 20190410 seg fault accessing/setting power_default_signal_toggle_rate
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2019-04-10 20:36:48 -07:00 |
|
James Cherry
|
e5c9bc43fd
|
2.0.10
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2019-03-12 17:25:53 -07:00 |
|
James Cherry
|
92f4968feb
|
write_path_spice bug fixes
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2019-01-20 09:44:24 -08:00 |
|
James Cherry
|
316742202f
|
sync
|
2019-01-16 15:37:31 -08:00 |
|
James Cherry
|
b075ccc783
|
update copyright
|
2019-01-01 12:26:11 -08:00 |
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James Cherry
|
f49dc75d32
|
sync
|
2018-12-05 14:18:41 -08:00 |
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James Cherry
|
2af22d9331
|
2018/10/23 read_verilog mod inst with no ports seg fault
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2018-10-23 16:24:22 -07:00 |
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James Cherry
|
1154fb89fd
|
and then there was light...
|
2018-09-28 08:54:21 -07:00 |