James Cherry
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78d29c8f90
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error/warn IDs
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2020-12-13 18:21:35 -07:00 |
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James Cherry
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52a4ce6b4c
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Network::libertyPort
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2020-11-11 10:01:15 -07:00 |
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James Cherry
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b3d8ae3d31
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gcc 9.1.0 warnings
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2020-11-09 19:44:50 -08:00 |
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James Cherry
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b57fcf173e
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leaks
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2020-09-05 17:20:21 -07:00 |
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James Cherry
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6d95ef44e5
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SdcNetwork::location(pin)
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2020-07-06 16:28:58 -07:00 |
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James Cherry
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2cab7b18e5
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Network::location(pin)
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2020-07-06 15:59:16 -07:00 |
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James Cherry
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27cc8f1614
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report_path -format json
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2020-07-06 15:18:13 -07:00 |
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James Cherry
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ee326f165c
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public headers in include/sta
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2020-04-05 14:53:44 -07:00 |
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James Cherry
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804953e317
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mv public headers to include/sta
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2020-04-05 11:35:51 -07:00 |
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James Cherry
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55a20c6830
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clearNetDrvPinrMap -> clearNetDrvrPinMap
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2020-03-15 20:05:30 -07:00 |
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James Cherry
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4a017e86eb
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update copyright
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2020-03-06 18:50:37 -08:00 |
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James Cherry
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3d6d6e9580
|
use #pragma once
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2020-02-15 17:13:16 -07:00 |
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James Cherry
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5edc2ba7ef
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groupBusPorts: sort memebers by bus index
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2020-02-01 17:38:33 -07:00 |
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James Cherry
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d22eaea30c
|
flush Makefile.am
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2020-01-04 19:00:51 -08:00 |
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James Cherry
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435bc2ba98
|
write_verilog bus ports missing bits
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2019-12-09 16:57:18 -07:00 |
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James Cherry
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ddb0c8dc58
|
hpin reorg code
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2019-11-18 19:29:36 -07:00 |
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James Cherry
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0c97a10f9a
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network external cell/port member vars
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2019-11-13 14:58:38 -07:00 |
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James Cherry
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3076b8d2ff
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VertexIndex -> VertexId
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2019-11-11 09:38:25 -07:00 |
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James Cherry
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184d044b02
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replace Pool with ObjectTable
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2019-11-11 08:28:42 -07:00 |
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James Cherry
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e7d8689f70
|
resizer support
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2019-11-05 10:14:35 -07:00 |
|
James Cherry
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6934b4ebcd
|
updates for resizer
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2019-11-05 07:51:54 -07:00 |
|
James Cherry
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6ac93c8c7d
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vertex_pin -> leaf_pin
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2019-10-25 08:51:59 -07:00 |
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James Cherry
|
3ae920be7d
|
write_verilog escaped bus name
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2019-08-13 21:34:35 -07:00 |
|
James Cherry
|
41ebd34031
|
leaks
|
2019-08-12 22:56:32 -07:00 |
|
James Cherry
|
db6b650a52
|
splash include git sha1
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2019-07-07 09:58:47 -07:00 |
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James Cherry
|
d7248abcab
|
sdc matches for verilog port nets like \foo[2] [0]
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2019-07-04 17:26:14 -07:00 |
|
James Cherry
|
74e287a7eb
|
write_verilog escaped bus port name "input [7:0] \in[0] ;"
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2019-07-03 21:18:38 -07:00 |
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James Cherry
|
7af69066df
|
VerilogWriter use liberty bus port order
|
2019-07-02 16:33:31 -07:00 |
|
James Cherry
|
eb9fdd1be0
|
write verilog match liberty bus bit order
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2019-07-02 07:07:34 -07:00 |
|
James Cherry
|
c759feaff6
|
SdcNetwork leak
|
2019-07-01 10:26:59 -07:00 |
|
James Cherry
|
8fa2dd674c
|
SdcNetwork memory error
|
2019-07-01 07:37:52 -07:00 |
|
James Cherry
|
ed6ed7c74b
|
g++ compile issue
|
2019-06-30 22:44:00 -07:00 |
|
James Cherry
|
f34fc4162d
|
base class destructors public virtual or protected non-virtual
|
2019-06-30 22:30:53 -07:00 |
|
James Cherry
|
d76ee0ca62
|
refactor SdcNetwork
|
2019-06-30 17:17:03 -07:00 |
|
James Cherry
|
93f5f9d664
|
no need for virtuals in Concrete network objects
|
2019-06-28 13:38:56 -07:00 |
|
James Cherry
|
88331ab9b1
|
Network bus brkts use library values
|
2019-06-28 11:51:43 -07:00 |
|
James Cherry
|
61333cd980
|
Network:bus_brkts_left/right
|
2019-06-26 17:14:31 -07:00 |
|
James Cherry
|
344394de29
|
link_design use verilog library to lookup top
|
2019-06-26 16:01:58 -07:00 |
|
James Cherry
|
e05e7185ba
|
report_checks transition_time field -> slew
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2019-06-24 08:35:04 -07:00 |
|
James Cherry
|
fef70f0983
|
ConcreteNetwork::replaceCell failed if port order differed cont.
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2019-06-21 12:50:57 -07:00 |
|
James Cherry
|
527b74b8e4
|
ConcreteNetwork::replaceCell failed if port order differed
|
2019-06-21 12:02:35 -07:00 |
|
James Cherry
|
96fcf1d8b2
|
ConcreteCell/Port pointers to corresponding liberty
|
2019-06-15 22:20:54 -07:00 |
|
James Cherry
|
dd8153c7f9
|
Network::isLeaf
|
2019-06-14 21:03:11 -07:00 |
|
James Cherry
|
9659c43590
|
network/sta replaceCell Cell support
|
2019-06-14 12:05:34 -07:00 |
|
James Cherry
|
cfaef559e6
|
replace_cell checks
|
2019-05-20 11:35:22 -06:00 |
|
James Cherry
|
a988588dac
|
sync
|
2019-05-19 17:06:06 -06:00 |
|
James Cherry
|
895c4c97c1
|
Sta::insert_buffer
|
2019-05-03 08:07:00 -07:00 |
|
James Cherry
|
2d519b4740
|
ucsd 20190410 seg fault accessing/setting power_default_signal_toggle_rate
|
2019-04-10 20:36:48 -07:00 |
|
James Cherry
|
e5c9bc43fd
|
2.0.10
|
2019-03-12 17:25:53 -07:00 |
|
James Cherry
|
dae85f08e0
|
misspelled "Deescription", gcc warnings
|
2019-03-03 17:50:56 -08:00 |