write_verilog bus ports missing bits
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a52877451d
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435bc2ba98
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@ -318,6 +318,7 @@ public:
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~BusPort();
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const char *name() const { return name_; }
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void pushMember(ConcretePort *port);
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void setFrom(int from);
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void setTo(int to);
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int from() const { return from_; }
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int to() const { return to_; }
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@ -357,6 +358,12 @@ BusPort::pushMember(ConcretePort *port)
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members_->push_back(port);
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}
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void
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BusPort::setFrom(int from)
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{
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from_ = from;
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}
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void
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BusPort::setTo(int to)
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{
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@ -376,10 +383,9 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
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// Remove bus bit ports from the ports_ vector during the scan by
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// keeping an index to the next insertion index and skipping over
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// the ones we want to remove.
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int port_index = 0;
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ConcretePortSeq::Iterator port_iter(ports_);
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while (port_iter.hasNext()) {
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ConcretePort *port = port_iter.next();
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ConcretePortSeq ports = ports_;
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ports_.clear();
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for (ConcretePort *port : ports) {
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const char *port_name = port->name();
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char *bus_name;
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int index;
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@ -389,7 +395,9 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
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if (!port->isBusBit()) {
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BusPort *bus_port = port_map.findKey(bus_name);
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if (bus_port) {
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bus_port->setTo(index);
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// Treat it as [max:min]/[from:to], ie downto.
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bus_port->setFrom(std::max(index, bus_port->from()));
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bus_port->setTo(std::min(index, bus_port->to()));
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stringDelete(bus_name);
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}
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else {
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@ -399,13 +407,11 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
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bus_port->pushMember(port);
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}
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else
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ports_[port_index++] = port;
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ports_.push_back(port);
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}
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else
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ports_[port_index++] = port;
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ports_.push_back(port);
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}
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// Resize to forget the ports that didn't make the cut.
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ports_.resize(port_index);
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// Make the bus ports.
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BusPortMap::Iterator bus_iter(port_map);
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@ -418,9 +424,7 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
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port->setDirection(bus_port->direction());
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delete bus_port;
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ConcretePortSeq::Iterator member_iter(members);
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while (member_iter.hasNext()) {
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ConcretePort *port = member_iter.next();
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for (ConcretePort *port : *members) {
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char *bus_name;
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int index;
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parseBusName(port->name(), bus_brkts_left, bus_brkts_right, escape_,
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