Bastian Koppelmann f9babcf666 port_data: Each submodule now specifies their bl/br names ... before the names of bl/br from the bitcell were assumed. If we want to allow renaming of bl/br from bitcells, we have to seperate the other modules from that. Note, that we don't touch every occurence of bl/br, but only the once necessary that pin renaming of the bitcell works. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>		2020-02-12 15:00:50 +01:00
..
pand2.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
pand3.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
pbuf.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
pdriver.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
pgate.py	Route to top of NMOS to prevent poly overlap nmos	2020-02-10 17:12:39 +00:00
pinv.py	Nwell fixes in pgates.	2020-02-06 16:20:09 +00:00
pinvbuf.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
pnand2.py	Move port 2 column address bus down.	2020-02-06 19:46:10 +00:00
pnand3.py	Force vertical vias on pnand3	2020-02-06 16:44:19 +00:00
pnor2.py	Nwell fixes in pgates.	2020-02-06 16:20:09 +00:00
precharge.py	bank: Connect instances by their individual bl/br names	2020-02-12 15:00:50 +01:00
ptristate_inv.py	Cleanup and rename vias.	2020-01-30 01:45:33 +00:00
ptx.py	Fix ptx so nmos and pmos have same active offset and gates align	2020-02-04 17:38:35 +00:00
pwrite_driver.py	Nwell fixes in pgates.	2020-02-06 16:20:09 +00:00
single_level_column_mux.py	port_data: Each submodule now specifies their bl/br names	2020-02-12 15:00:50 +01:00