mrg 4be075e586 Overlap length can include a rectangle overlap.

2022-05-16 14:57:32 -07:00

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channel_route.py

Remove breakpoint

2022-03-07 16:59:55 -08:00

contact.py

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custom_cell_properties.py

Rework replica_bitcell_array supplies

2022-04-19 08:50:11 -07:00

custom_layer_properties.py

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delay_data.py

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design.py

Move power supply stack to design

2022-02-18 15:02:45 -08:00

errors.py

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geometry.py

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hierarchy_design.py

Don't double prefix a name

2022-05-13 14:32:52 -07:00

hierarchy_layout.py

Add min area metal in preferred direction

2022-05-11 10:50:32 -07:00

hierarchy_spice.py

Add per tool lvs directories

2021-12-17 10:21:34 -08:00

lef.py

Intersection now returns a pin_layout fixed during LEF computation.

2022-05-13 13:56:16 -07:00

pin_layout.py

Overlap length can include a rectangle overlap.

2022-05-16 14:57:32 -07:00

power_data.py

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route.py

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timing_graph.py

Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage.

2021-09-07 15:56:27 -07:00

utils.py

fix bias correspondence points

2021-06-30 05:21:39 -07:00

vector.py

PEP8 cleanup

2021-09-07 16:49:44 -07:00

verilog.py

Move mem reg before usage for compatibility

2021-10-13 09:46:02 -07:00

wire_path.py

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wire_spice_model.py

Added unit r and c values with m2 minwidth incorporated to match CACTI params

2021-08-01 00:23:59 -07:00

wire.py

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