mrg af4ed3dd6e Skip riscv func test for time sake		2020-06-26 06:50:45 -07:00
..
base	Always route the channel route since it is it's own design.	2020-06-25 17:43:44 -07:00
bitcells	Error out on single port in sky130	2020-06-22 15:41:59 -07:00
characterizer	ngspice raw save doesn't work with measures	2020-06-19 07:09:15 -07:00
custom	Change s8 to sky130	2020-06-12 14:23:26 -07:00
datasheet	Convert capital names to lower case for consistency	2019-08-21 13:45:34 -07:00
drc	PEP8 cleanup	2020-04-15 11:24:28 -07:00
example_configs	revert example scn4m to non netlist only	2020-02-09 23:52:11 -08:00
gdsMill	added purposes to addText(), removed reference to specific tech from gdsMill	2020-02-19 16:26:52 -08:00
modules	Col decoders are anything not bitcell pitch.	2020-06-25 14:25:48 -07:00
pgates	Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev	2020-06-25 08:57:37 -07:00
router	Changes to simplify metal preferred directions and pitches.	2020-05-10 11:32:45 -07:00
sram	Add riscv unit tests	2020-06-25 15:34:18 -07:00
tests	Skip riscv func test for time sake	2020-06-26 06:50:45 -07:00
verify	Disable magic filter in sky130	2020-06-22 16:58:01 -07:00
Makefile	…
debug.py	Add layer-purpose GDS support. Various PEP8 fixes.	2019-11-14 18:17:20 +00:00
gen_stimulus.py	Fixed errors in extra rows characterization	2020-03-22 20:54:49 +00:00
globals.py	Change s8 to sky130	2020-06-12 14:23:26 -07:00
openram.py	Characterization for extra rows	2020-02-20 17:01:52 +00:00
options.py	move accuracy_requirement from techfile to config	2020-06-25 06:44:07 -07:00
run_profile.sh	Convert pin map to a set for faster membership.	2019-04-01 15:45:44 -07:00
sram_factory.py	Auto-generate port dependent cell names.	2020-06-05 15:09:22 -07:00
view_profile.py	Remove some flake8 errors/warnings.	2019-10-02 23:26:02 +00:00