mrg acfec369d6 Add ptx cell properties

2020-10-28 09:54:15 -07:00

..

base

Add ptx cell properties

2020-10-28 09:54:15 -07:00

bitcells

Add ptx cell properties

2020-10-28 09:54:15 -07:00

characterizer

Require either device models or device library. Remove sky130 flag.

2020-10-23 14:07:26 -07:00

custom

move sky130 specific stuff to tech module lib

2020-10-13 04:48:10 -07:00

datasheet

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drc

PEP8 cleanup

2020-04-15 11:24:28 -07:00

example_configs

Remove extraneous config files.

2020-10-23 13:56:27 -07:00

gdsMill

Search all shapes for boundary rather than specify structure

2020-10-08 14:04:19 -07:00

modules

Add ptx cell properties

2020-10-28 09:54:15 -07:00

pgates

Add ptx cell properties

2020-10-28 09:54:15 -07:00

riscv

single port progess

2020-09-14 18:11:38 -07:00

router

Names in skiptests changed. Reduce grid router verbosity.

2020-10-23 09:22:59 -07:00

sram

Allow 16-way column mux

2020-10-06 16:27:02 -07:00

tests

Names in skiptests changed. Reduce grid router verbosity.

2020-10-23 09:22:59 -07:00

verify

Initial pex sram test.

2020-10-02 13:32:52 -07:00

debug.py

DRC/LVS and errors fixes.

2020-06-30 07:16:05 -07:00

gen_stimulus.py

Fixed errors in extra rows characterization

2020-03-22 20:54:49 +00:00

globals.py

Don't use single slew for nominal corner

2020-10-16 16:51:28 -07:00

Makefile

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openram.py

Add words_per_row and others in config file.

2020-07-13 12:37:56 -07:00

options.py

Add load/slew scale option to config files

2020-10-16 13:52:36 -07:00

run_profile.sh

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sram_factory.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

view_profile.py

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