OpenRAM/compiler/modules
mrg 0100ae57a3 Fix mirror with odd number of rows 2020-12-08 10:31:22 -08:00
..
and2_dec.py Use custom cells when needed. 2020-11-03 11:58:25 -08:00
and3_dec.py Use custom cells when needed. 2020-11-03 11:58:25 -08:00
and4_dec.py Use custom cells when needed. 2020-11-03 11:58:25 -08:00
bank.py Change layer away from wordlines 2020-12-01 11:33:55 -08:00
bank_select.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
bitcell_array.py Rework bitcells. 2020-11-13 10:07:40 -08:00
bitcell_base_array.py Many edits. 2020-11-22 08:24:47 -08:00
col_cap_array.py Use internal name for col/row caps. gds ordered read enabled. 2020-12-03 10:03:47 -08:00
column_mux_array.py Fix select layer for column mux array 2020-12-01 15:20:44 -08:00
control_logic.py Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
delay_chain.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
dff_array.py Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
dff_buf.py Small bug fixes related to new name mapping. 2020-11-16 13:42:42 -08:00
dff_buf_array.py Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
dff_inv.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
dff_inv_array.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
dummy_array.py Add bl/br pins to dummy array 2020-11-12 12:38:09 -08:00
global_bitcell_array.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
hierarchical_decoder.py Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
hierarchical_predecode.py Remove via-to-via path width hack 2020-12-01 13:27:32 -08:00
hierarchical_predecode2x4.py Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
hierarchical_predecode3x8.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
hierarchical_predecode4x16.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
local_bitcell_array.py Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
module_type.py Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
multibank.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
orig_bitcell_array.py Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
port_address.py Fix wrong via starting layer 2020-12-01 17:12:35 -08:00
port_data.py Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
precharge_array.py Fix pbitcell erros 2020-11-13 15:55:55 -08:00
replica_bitcell_array.py Fix mirror with odd number of rows 2020-12-08 10:31:22 -08:00
replica_column.py Fix iteration bug with new type 2020-11-20 17:33:15 -08:00
row_cap_array.py Use internal name for col/row caps. gds ordered read enabled. 2020-12-03 10:03:47 -08:00
sense_amp_array.py Fix pbitcell erros 2020-11-13 15:55:55 -08:00
tri_gate_array.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
wordline_buffer_array.py Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
wordline_driver_array.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
write_driver_array.py Fix pbitcell erros 2020-11-13 15:55:55 -08:00
write_mask_and_array.py Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00