mirror of https://github.com/VLSIDA/OpenRAM.git
362 lines
16 KiB
Python
362 lines
16 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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import math
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from vector import vector
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from sram_factory import factory
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from globals import OPTS
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from tech import layer_properties as layer_props
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class hierarchical_predecode(design.design):
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"""
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Pre 2x4 and 3x8 and TBD 4x16 decoder shared code.
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"""
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def __init__(self, name, input_number, height=None):
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self.number_of_inputs = input_number
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b = factory.create(module_type=OPTS.bitcell)
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if not height:
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self.cell_height = b.height
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self.column_decoder = False
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else:
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self.cell_height = height
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# If we are pitch matched to the bitcell, it's a predecoder
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# otherwise it's a column decoder (out of pgates)
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self.column_decoder = (height != b.height)
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self.number_of_outputs = int(math.pow(2, self.number_of_inputs))
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super().__init__(name)
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def add_pins(self):
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for k in range(self.number_of_inputs):
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self.add_pin("in_{0}".format(k), "INPUT")
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for i in range(self.number_of_outputs):
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self.add_pin("out_{0}".format(i), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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""" Add the INV and AND gate modules """
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debug.check(self.number_of_inputs <= 4,
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"Invalid number of predecode inputs: {}".format(self.number_of_inputs))
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if self.column_decoder:
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and_type = "pand{}".format(self.number_of_inputs)
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inv_type = "pinv"
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else:
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and_type = "and{}_dec".format(self.number_of_inputs)
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inv_type = "inv_dec"
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self.and_mod = factory.create(module_type=and_type,
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height=self.cell_height)
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self.add_mod(self.and_mod)
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# This uses the pinv_dec parameterized cell
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self.inv = factory.create(module_type=inv_type,
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height=self.cell_height,
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size=1)
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self.add_mod(self.inv)
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def create_layout(self):
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""" The general organization is from left to right:
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1) a set of M2 rails for input signals
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2) a set of inverters to invert input signals
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3) a set of M2 rails for the vdd, gnd, inverted inputs, inputs
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4) a set of AND gates for inversion
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"""
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self.setup_layout_constraints()
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self.route_rails()
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self.place_input_inverters()
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self.place_and_array()
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self.route()
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self.add_boundary()
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self.DRC_LVS()
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def setup_layout_constraints(self):
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# Inputs to cells are on input layer
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# Outputs from cells are on output layer
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self.bus_layer = layer_props.hierarchical_predecode.bus_layer
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self.bus_directions = layer_props.hierarchical_predecode.bus_directions
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self.bus_pitch = getattr(self, self.bus_layer + "_pitch")
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self.bus_space = layer_props.hierarchical_predecode.bus_space_factor * getattr(self, self.bus_layer + "_space")
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self.input_layer = layer_props.hierarchical_predecode.input_layer
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self.output_layer = layer_props.hierarchical_predecode.output_layer
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self.output_layer_pitch = getattr(self, self.output_layer + "_pitch")
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self.height = self.number_of_outputs * self.and_mod.height
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# x offset for input inverters
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# +1 input for spacing for supply rail contacts
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self.x_off_inv_1 = (self.number_of_inputs + 1) * self.bus_pitch + self.bus_pitch
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# x offset to AND decoder includes the left rails, mid rails and inverters, plus two extra bus pitches
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self.x_off_and = self.x_off_inv_1 + self.inv.width + (2 * self.number_of_inputs + 2) * self.bus_pitch
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# x offset to output inverters
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self.width = self.x_off_and + self.and_mod.width
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def route_rails(self):
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""" Create all of the rails for the inputs and vdd/gnd/inputs_bar/inputs """
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input_names = ["in_{}".format(x) for x in range(self.number_of_inputs)]
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# Offsets for the perimeter spacing to other modules
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# This uses m3 pitch to leave space for power routes
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offset = vector(self.bus_pitch, self.bus_pitch)
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self.input_rails = self.create_vertical_bus(layer=self.bus_layer,
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offset=offset,
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names=input_names,
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length=self.height - 2 * self.bus_pitch)
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invert_names = ["Abar_{}".format(x) for x in range(self.number_of_inputs)]
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non_invert_names = ["A_{}".format(x) for x in range(self.number_of_inputs)]
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decode_names = invert_names + non_invert_names
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offset = vector(self.x_off_inv_1 + self.inv.width + self.bus_pitch, self.bus_pitch)
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self.decode_rails = self.create_vertical_bus(layer=self.bus_layer,
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offset=offset,
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names=decode_names,
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length=self.height - 2 * self.bus_pitch)
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def create_input_inverters(self):
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""" Create the input inverters to invert input signals for the decode stage. """
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self.inv_inst = []
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for inv_num in range(self.number_of_inputs):
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name = "pre_inv_{0}".format(inv_num)
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self.inv_inst.append(self.add_inst(name=name,
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mod=self.inv))
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self.connect_inst(["in_{0}".format(inv_num),
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"inbar_{0}".format(inv_num),
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"vdd", "gnd"])
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def place_input_inverters(self):
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""" Place the input inverters to invert input signals for the decode stage. """
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for inv_num in range(self.number_of_inputs):
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if (inv_num % 2 == 0):
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y_off = inv_num * (self.inv.height)
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mirror = "R0"
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else:
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y_off = (inv_num + 1) * (self.inv.height)
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mirror="MX"
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offset = vector(self.x_off_inv_1, y_off)
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self.inv_inst[inv_num].place(offset=offset,
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mirror=mirror)
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def create_and_array(self, connections):
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""" Create the AND stage for the decodes """
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self.and_inst = []
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for and_input in range(self.number_of_outputs):
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inout = str(self.number_of_inputs) + "x" + str(self.number_of_outputs)
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name = "Xpre{0}_and_{1}".format(inout, and_input)
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self.and_inst.append(self.add_inst(name=name,
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mod=self.and_mod))
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self.connect_inst(connections[and_input])
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def place_and_array(self):
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""" Place the AND stage for the decodes """
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for and_input in range(self.number_of_outputs):
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# inout = str(self.number_of_inputs) + "x" + str(self.number_of_outputs)
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if (and_input % 2 == 0):
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y_off = and_input * self.and_mod.height
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mirror = "R0"
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else:
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y_off = (and_input + 1) * self.and_mod.height
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mirror = "MX"
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offset = vector(self.x_off_and, y_off)
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self.and_inst[and_input].place(offset=offset,
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mirror=mirror)
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def route(self):
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self.route_input_inverters()
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self.route_inputs_to_rails()
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self.route_and_to_rails()
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self.route_output_and()
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self.route_vdd_gnd()
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def route_inputs_to_rails(self):
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""" Route the uninverted inputs to the second set of rails """
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top_and_gate = self.and_inst[-1]
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for num in range(self.number_of_inputs):
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if num == 0:
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pin = top_and_gate.get_pin("A")
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elif num == 1:
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pin = top_and_gate.get_pin("B")
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elif num == 2:
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pin = top_and_gate.get_pin("C")
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elif num == 3:
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pin = top_and_gate.get_pin("D")
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else:
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debug.error("Too many inputs for predecoder.", -1)
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y_offset = pin.cy()
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in_pin = "in_{}".format(num)
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a_pin = "A_{}".format(num)
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in_pos = vector(self.input_rails[in_pin].cx(), y_offset)
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a_pos = vector(self.decode_rails[a_pin].cx(), y_offset)
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self.add_path(self.input_layer, [in_pos, a_pos])
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self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=[self.input_rails[in_pin].cx(), y_offset])
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self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=[self.decode_rails[a_pin].cx(), y_offset])
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def route_output_and(self):
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"""
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Route all conections of the outputs and gates
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"""
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for num in range(self.number_of_outputs):
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z_pin = self.and_inst[num].get_pin("Z")
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self.add_layout_pin(text="out_{}".format(num),
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layer=z_pin.layer,
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offset=z_pin.ll(),
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height=z_pin.height(),
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width=z_pin.width())
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def route_input_inverters(self):
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"""
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Route all conections of the inputs inverters [Inputs, outputs, vdd, gnd]
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"""
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for inv_num in range(self.number_of_inputs):
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out_pin = "Abar_{}".format(inv_num)
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in_pin = "in_{}".format(inv_num)
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inv_out_pin = self.inv_inst[inv_num].get_pin("Z")
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# add output so that it is just below the vdd or gnd rail
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# since this is where the p/n devices are and there are no
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# pins in the and gates.
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inv_out_pos = inv_out_pin.rc()
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y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch
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right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0)
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rail_pos = vector(self.decode_rails[out_pin].cx(), y_offset)
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self.add_path(self.output_layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos])
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self.add_via_stack_center(from_layer=inv_out_pin.layer,
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to_layer=self.output_layer,
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offset=inv_out_pos)
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self.add_via_stack_center(from_layer=self.output_layer,
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to_layer=self.bus_layer,
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offset=rail_pos,
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directions=self.bus_directions)
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# route input
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pin = self.inv_inst[inv_num].get_pin("A")
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inv_in_pos = pin.center()
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in_pos = vector(self.input_rails[in_pin].cx(), inv_in_pos.y)
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self.add_path(self.input_layer, [in_pos, inv_in_pos])
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self.add_via_stack_center(from_layer=pin.layer,
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to_layer=self.input_layer,
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offset=inv_in_pos)
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via=self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=in_pos)
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# Create the input pin at this location on the rail
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self.add_layout_pin_rect_center(text=in_pin,
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layer=self.bus_layer,
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offset=in_pos,
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height=via.mod.second_layer_height,
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width=via.mod.second_layer_width)
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# This is a hack to fix via-to-via spacing issues, but it is currently
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# causing its own DRC problems.
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# if layer_props.hierarchical_predecode.vertical_supply:
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# below_rail = vector(self.decode_rails[out_pin].cx(), y_offset - (self.cell_height / 2))
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# self.add_path(self.bus_layer, [rail_pos, below_rail], width=self.li_width + self.m1_enclose_mcon * 2)
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def route_and_to_rails(self):
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# This 2D array defines the connection mapping
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and_input_line_combination = self.get_and_input_line_combination()
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for k in range(self.number_of_outputs):
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# create x offset list
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index_lst= and_input_line_combination[k]
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if self.number_of_inputs == 2:
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gate_lst = ["A", "B"]
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elif self.number_of_inputs == 3:
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gate_lst = ["A", "B", "C"]
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elif self.number_of_inputs == 4:
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gate_lst = ["A", "B", "C", "D"]
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else:
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debug.error("Invalid number of nand inputs for decode", -1)
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# this will connect pins A,B or A,B,C or A,B,C,D
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for rail_pin, gate_pin in zip(index_lst, gate_lst):
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pin = self.and_inst[k].get_pin(gate_pin)
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pin_pos = pin.center()
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rail_pos = vector(self.decode_rails[rail_pin].cx(), pin_pos.y)
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self.add_path(self.input_layer, [rail_pos, pin_pos])
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self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=rail_pos,
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directions=self.bus_directions)
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if gate_pin == "A":
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direction = None
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else:
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direction = ("H", "H")
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self.add_via_stack_center(from_layer=pin.layer,
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to_layer=self.input_layer,
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offset=pin_pos,
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directions=direction)
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def route_vdd_gnd(self):
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""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
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# We may ahve vertical power supply rails
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if layer_props.hierarchical_predecode.vertical_supply and not self.column_decoder:
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for n in ["vdd", "gnd"]:
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# This makes a wire from top to bottom for both inv and and gates
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for i in [self.inv_inst, self.and_inst]:
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bot_pins = i[0].get_pins(n)
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top_pins = i[-1].get_pins(n)
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for (bot_pin, top_pin) in zip(bot_pins, top_pins):
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self.add_rect(layer=bot_pin.layer,
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offset=vector(bot_pin.lx(), self.bus_pitch),
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width=bot_pin.width(),
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height=top_pin.uy() - self.bus_pitch)
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# This adds power vias at the top of each cell
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# (except the last to keep them inside the boundary)
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for i in self.inv_inst[:-1:2] + self.and_inst[:-1:2]:
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pins = i.get_pins(n)
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for pin in pins:
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self.add_power_pin(name=n,
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loc=pin.uc(),
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start_layer=pin.layer)
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self.add_power_pin(name=n,
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loc=pin.uc(),
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start_layer=pin.layer)
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# In other techs, we are using standard cell decoder cells with horizontal power
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else:
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for num in range(0, self.number_of_outputs):
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# Route both supplies
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for n in ["vdd", "gnd"]:
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and_pins = self.and_inst[num].get_pins(n)
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for and_pin in and_pins:
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self.add_segment_center(layer=and_pin.layer,
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start=vector(0, and_pin.cy()),
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end=vector(self.width, and_pin.cy()))
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# Add pins in two locations
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for xoffset in [self.inv_inst[0].lx() - self.bus_space,
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self.and_inst[0].lx() - self.bus_space]:
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pin_pos = vector(xoffset, and_pin.cy())
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self.add_power_pin(name=n,
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loc=pin_pos,
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start_layer=and_pin.layer)
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