Matt Guthaus 87f539f3a8 Separate netlist/layout for flop and precharge array.

2018-08-27 10:54:21 -07:00

..

base

Add place_inst routine.

2018-08-27 10:42:40 -07:00

characterizer

Remove OEB signal since we split DIN/DOUT ports

2018-08-13 14:09:49 -07:00

gdsMill

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

modules

Separate netlist/layout for flop and precharge array.

2018-08-27 10:54:21 -07:00

pgates

Changing function names in bitcell and pbitcell to better reflect what values they're returning. Editting function calls in bitcell_array and bank accordingly.

2018-08-26 14:37:17 -07:00

router

Fix unit tests to be DRC clean.

2017-06-07 10:29:53 -07:00

tests

Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines.

2018-08-18 15:27:07 -07:00

verify

Updated to include local magic rules

2018-08-15 09:46:23 -07:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Fix num words in example.

2018-02-23 12:17:43 -08:00

example_config_scn3me_subm.py

Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library.

2018-02-12 11:22:47 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Only print LVS/DRC stats when it is enabled

2018-07-25 13:44:34 -07:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

openram.py

Improve openram output. Fix save output function name.

2018-07-12 10:35:38 -07:00

options.py

Fix options so it is in /tmp in RAM drive

2018-07-05 16:33:26 -07:00

sram_1bank.py

made multi-port changes to sram. This commit will allow all levels of openram to pass unit tests

2018-08-20 22:11:24 -07:00

sram_2bank.py

Add LVS correspondence points to each bank type

2018-07-18 14:29:04 -07:00

sram_4bank.py

Add LVS correspondence points to each bank type

2018-07-18 14:29:04 -07:00

sram_base.py

Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port

2018-08-18 16:51:21 -07:00

sram.py

Add verilog_write to sram wrapper for verilog unit test

2018-07-19 10:05:30 -07:00