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channel_route.py
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Remove breakpoint
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2022-03-07 16:59:55 -08:00 |
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contact.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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custom_cell_properties.py
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Rework replica_bitcell_array supplies
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2022-04-19 08:50:11 -07:00 |
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custom_layer_properties.py
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fix freepdk45
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2021-06-17 03:21:01 -07:00 |
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delay_data.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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design.py
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Move power supply stack to design
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2022-02-18 15:02:45 -08:00 |
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errors.py
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Add exception errors file
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2020-04-08 16:55:45 -07:00 |
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geometry.py
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Merge remote-tracking branch 'bvhoof/dev' into dev
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2021-03-01 12:16:26 -08:00 |
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hierarchy_design.py
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By default uniquify instances based on macro name.
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2022-03-11 18:01:45 -08:00 |
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hierarchy_layout.py
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Rework replica_bitcell_array supplies
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2022-04-19 08:50:11 -07:00 |
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hierarchy_spice.py
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Add per tool lvs directories
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2021-12-17 10:21:34 -08:00 |
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lef.py
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Improve supply routing for ring and side pins
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2021-05-28 10:58:30 -07:00 |
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pin_layout.py
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don't use hard coded purpose numbers
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2021-07-01 17:31:01 -07:00 |
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power_data.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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route.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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timing_graph.py
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Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage.
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2021-09-07 15:56:27 -07:00 |
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utils.py
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fix bias correspondence points
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2021-06-30 05:21:39 -07:00 |
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vector.py
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PEP8 cleanup
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2021-09-07 16:49:44 -07:00 |
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verilog.py
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Move mem reg before usage for compatibility
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2021-10-13 09:46:02 -07:00 |
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wire.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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wire_path.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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wire_spice_model.py
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Added unit r and c values with m2 minwidth incorporated to match CACTI params
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2021-08-01 00:23:59 -07:00 |
64f2f90664