Matt Guthaus 6c9ae1c659 Remove temp names in DRC/LVS. Extract unique doesn't actually extract.

2019-02-24 07:26:21 -08:00

..

base

Remove temp names in DRC/LVS. Extract unique doesn't actually extract.

2019-02-24 07:26:21 -08:00

bitcells

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

characterizer

Revert bus bits back into pins

2019-02-22 16:22:27 -08:00

datasheet

fixed area not being found

2019-02-14 07:01:35 -08:00

drc

Moving wide metal spacing to routing grid level

2018-10-15 09:59:16 -07:00

example_configs

Move inspect into if statement for runtime

2019-01-30 08:42:25 -08:00

gdsMill

Remove non-rectangular error and just skip them.

2019-01-30 10:25:01 -08:00

modules

Changed test values to fix tests.

2019-02-06 15:27:29 -08:00

pgates

Fixed some delay model bugs.

2019-02-05 21:15:12 -08:00

router

Check membership of keys without using keys() list

2019-01-30 13:02:34 -08:00

tests

Merge branch 'magic_lvs_ports' into dev

2019-02-22 19:02:43 -08:00

verify

Remove temp names in DRC/LVS. Extract unique doesn't actually extract.

2019-02-24 07:26:21 -08:00

debug.py

Add missing / in output path for log

2019-02-21 10:23:30 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

git_id

track git_id

2018-12-05 16:13:52 -08:00

globals.py

Merge remote-tracking branch 'origin/dev' into factory

2019-01-18 09:52:18 -08:00

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

complete log file generation

2019-01-13 14:34:46 -08:00

options.py

Fixed merge conflicts

2019-01-28 22:33:08 -08:00

profile_stats.py

Add profile scripts

2018-12-07 08:56:40 -08:00

run_profile.sh

Move inspect into if statement for runtime

2019-01-30 08:42:25 -08:00

sram_1bank.py

Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.

2019-01-11 14:15:16 -08:00

sram_2bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_base.py

Change pbuf/pinv to pdriver in control logic.

2019-01-23 12:03:52 -08:00

sram_config.py

Added word per row to sram config with a default arguement to fix test.

2019-01-30 11:43:47 -08:00

sram_factory.py

Added some comments to the spice files.

2019-01-25 15:00:00 -08:00

sram.py

html datasheet no longer dependeds on sram

2019-01-16 14:52:01 -08:00

view_profile.py

Convert source and target lists to sets for faster contains check.

2019-01-30 11:15:47 -08:00