mirror of https://github.com/VLSIDA/OpenRAM.git
656fdd1008
both functions share a lot of code and are passing around a lot of data
under similar names (inst1, inst1_start_bit, inst1_bl_name, ...). Thus
we group all these elements in a named tuple to ease passing around
these elements.
All callers of channel_route/connect_bitlines() either pass in the bl/br
names or rely on "br_{}"/"bl_{}" as defaults. These hard coded values
should be determined by the instances. Thus we get the bitline names
based on the instances passed in. The callers only provide a template
string, to take care of the case that bitlines are called "bl_out_{}".
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
|
||
|---|---|---|
| .. | ||
| base | ||
| bitcells | ||
| characterizer | ||
| datasheet | ||
| drc | ||
| example_configs | ||
| gdsMill | ||
| modules | ||
| pgates | ||
| router | ||
| sram | ||
| tests | ||
| verify | ||
| Makefile | ||
| debug.py | ||
| gen_stimulus.py | ||
| globals.py | ||
| openram.py | ||
| options.py | ||
| run_profile.sh | ||
| sram_factory.py | ||
| view_profile.py | ||