Matt Guthaus 63a8f7c653 Remove m2 from write driver

2018-04-16 16:15:35 -07:00

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base

Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.

2018-03-23 08:14:09 -07:00

characterizer

Fixed accidental changes made to analytical delay.

2018-02-28 12:18:41 -08:00

gdsMill

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modules

Remove m2 from write driver

2018-04-16 16:15:35 -07:00

pgates

Move precharge and column mux cells to pgate directory.

2018-04-06 17:15:14 -07:00

router

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tests

Move precharge and column mux cells to pgate directory.

2018-04-06 17:15:14 -07:00

verify

Add bank_sel to bank_select module as input.

2018-03-23 08:13:39 -07:00

debug.py

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example_config_freepdk45.py

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example_config_scn3me_subm.py

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gen_stimulus.py

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globals.py

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Makefile

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openram.py

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options.py

Add local dir for output. Will remove later.

2018-04-04 09:55:32 -07:00

regress.sh

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sram.py

Mostly working for 1 bank.

2018-03-23 08:14:26 -07:00