luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
468a759d1e99ad270e75b77164ea6dfb4206fbeb
OpenRAM/compiler/tests
T
History
Matt Guthaus 468a759d1e Fixed control problems (probably) 
Extended functional tests for 15 cycles (slow, but more checking)
Fixed s_en to be gated AFTER the RBL.
2019-07-27 11:09:08 -07:00
..
golden
Reapply jsowash update without spice model file
2019-06-24 08:59:58 -07:00
00_code_format_check_test.py
Merge branch 'pep8_cleanup' into dev
2019-06-14 08:47:10 -07:00
01_library_drc_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
02_library_lvs_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
03_contact_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
03_path_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
03_ptx_1finger_nmos_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
03_ptx_1finger_pmos_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
03_ptx_3finger_nmos_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
03_ptx_3finger_pmos_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
03_ptx_4finger_nmos_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
03_ptx_4finger_pmos_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
03_wire_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_dummy_pbitcell_test.py
Replica bitcell array with arbitrary RBLs working
2019-07-10 15:56:51 -07:00
04_pand2_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_pbitcell_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_pbuf_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_pdriver_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_pinv_1x_beta_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_pinv_1x_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_pinv_2x_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_pinv_10x_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_pinvbuf_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_pnand2_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_pnand3_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_pnor2_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_precharge_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_replica_pbitcell_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
04_single_level_column_mux_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
05_bitcell_1rw_1r_array_test.py
Clean up multiport test options to be consistent.
2019-07-12 10:39:55 -07:00
05_bitcell_array_test.py
Merge branch 'dev' into rbl_revamp
2019-07-03 14:05:28 -07:00
05_dummy_array_test.py
Re-enable replica tests
2019-07-03 14:57:47 -07:00
05_pbitcell_array_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
05_replica_pbitcell_array_test.py
Add pbitcell RW test
2019-07-16 11:54:39 -07:00
06_hierarchical_decoder_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
06_hierarchical_predecode2x4_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
06_hierarchical_predecode3x8_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
07_single_level_column_mux_array_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
08_precharge_array_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
08_wordline_driver_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
09_sense_amp_array_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
10_write_driver_array_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
11_dff_array_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
11_dff_buf_array_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
11_dff_buf_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
12_tri_gate_array_test.py
Merge branch 'dev' into rbl_revamp
2019-07-03 14:05:28 -07:00
13_delay_chain_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
14_replica_bitcell_1rw_1r_array_test.py
Remove old replica bitline.
2019-07-18 15:19:40 -07:00
14_replica_bitcell_array_test.py
Remove old replica bitline.
2019-07-18 15:19:40 -07:00
14_replica_column_test.py
Remove old replica bitline.
2019-07-18 15:19:40 -07:00
16_control_logic_multiport_test.py
Removed write_size from parameters.
2019-07-21 15:53:05 -07:00
16_control_logic_test.py
Fix bitline names in merge error
2019-07-26 22:03:50 -07:00
18_port_address_test.py
Create port address module
2019-07-05 09:03:52 -07:00
18_port_data_test.py
Single banks working with new RBL
2019-07-11 14:47:27 -07:00
19_bank_select_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
19_multi_bank_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
19_pmulti_bank_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
19_psingle_bank_test.py
Cleanup unit test. Fix s_en control bug for r-only.
2019-07-16 13:51:31 -07:00
19_single_bank_1rw_1r_test.py
Clean up multiport test options to be consistent.
2019-07-12 10:39:55 -07:00
19_single_bank_1w_1r_test.py
Cleanup unit test. Fix s_en control bug for r-only.
2019-07-16 13:51:31 -07:00
19_single_bank_test.py
Single banks working with new RBL
2019-07-11 14:47:27 -07:00
20_psram_1bank_2mux_1rw_1w_test.py
Clean up multiport test options to be consistent.
2019-07-12 10:39:55 -07:00
20_psram_1bank_2mux_1w_1r_test.py
Clean up multiport test options to be consistent.
2019-07-12 10:39:55 -07:00
20_psram_1bank_2mux_test.py
Clean up multiport test options to be consistent.
2019-07-12 10:39:55 -07:00
20_psram_1bank_4mux_1rw_1r_test.py
Clean up multiport test options to be consistent.
2019-07-12 10:39:55 -07:00
20_sram_1bank_2mux_1rw_1r_test.py
Clean up multiport test options to be consistent.
2019-07-12 10:39:55 -07:00
20_sram_1bank_2mux_1w_1r_test.py
Clean up multiport test options to be consistent.
2019-07-12 10:39:55 -07:00
20_sram_1bank_2mux_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
20_sram_1bank_4mux_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
20_sram_1bank_8mux_1rw_1r_test.py
Clean up multiport test options to be consistent.
2019-07-12 10:39:55 -07:00
20_sram_1bank_8mux_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
20_sram_1bank_nomux_1rw_1r_test.py
Clean up multiport test options to be consistent.
2019-07-12 10:39:55 -07:00
20_sram_1bank_nomux_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
20_sram_2bank_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
21_hspice_delay_test.py
Fix some regression fails.
2019-07-25 14:18:08 -07:00
21_hspice_setuphold_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
21_model_delay_test.py
Minor cleanup. Skip more tests until analytical fixed.
2019-07-26 08:33:06 -07:00
21_ngspice_delay_test.py
Fix some regression fails.
2019-07-25 14:18:08 -07:00
21_ngspice_setuphold_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
22_psram_1bank_2mux_func_test.py
Fixed control problems (probably)
2019-07-27 11:09:08 -07:00
22_psram_1bank_4mux_func_test.py
Fixed control problems (probably)
2019-07-27 11:09:08 -07:00
22_psram_1bank_8mux_func_test.py
Fixed control problems (probably)
2019-07-27 11:09:08 -07:00
22_psram_1bank_nomux_func_test.py
Fixed control problems (probably)
2019-07-27 11:09:08 -07:00
22_psram_wmask_func_test.py
Fixed control problems (probably)
2019-07-27 11:09:08 -07:00
22_sram_1bank_2mux_func_test.py
Fixed control problems (probably)
2019-07-27 11:09:08 -07:00
22_sram_1bank_4mux_func_test.py
Fixed control problems (probably)
2019-07-27 11:09:08 -07:00
22_sram_1bank_8mux_func_test.py
Fixed control problems (probably)
2019-07-27 11:09:08 -07:00
22_sram_1bank_nomux_func_test.py
Fixed control problems (probably)
2019-07-27 11:09:08 -07:00
22_sram_1rw_1r_1bank_nomux_func_test.py
Fixed control problems (probably)
2019-07-27 11:09:08 -07:00
22_sram_wmask_func_test.py
Fixed control problems (probably)
2019-07-27 11:09:08 -07:00
23_lib_sram_model_corners_test.py
Skip model tests for now
2019-07-25 14:46:33 -07:00
23_lib_sram_model_test.py
Skip model tests for now
2019-07-25 14:46:33 -07:00
23_lib_sram_prune_test.py
Skip prune test for now
2019-07-25 14:49:11 -07:00
23_lib_sram_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
24_lef_sram_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
25_verilog_sram_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
26_hspice_pex_pinv_test.py
fix the delay measure bug in pex tests
2019-07-10 04:39:40 -07:00
26_ngspice_pex_pinv_test.py
fix the delay measure bug in pex tests
2019-07-10 04:39:40 -07:00
26_pex_test.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
30_openram_back_end_test.py
Minor cleanup. Skip more tests until analytical fixed.
2019-07-26 08:33:06 -07:00
30_openram_front_end_test.py
Minor cleanup. Skip more tests until analytical fixed.
2019-07-26 08:33:06 -07:00
config_freepdk45_back_end.py
Use non-analytical models for now
2019-07-25 14:55:42 -07:00
config_freepdk45_front_end.py
Use non-analytical models for now
2019-07-25 14:55:42 -07:00
config_freepdk45.py
Fix space before comment
2019-06-14 08:43:41 -07:00
config_scn3me_subm_back_end.py
Use non-analytical models for now
2019-07-25 14:55:42 -07:00
config_scn3me_subm_front_end.py
Use non-analytical models for now
2019-07-25 14:55:42 -07:00
config_scn3me_subm.py
Remove useless comments. Add missing copyright.
2019-06-14 10:13:13 -07:00
config_scn4m_subm_back_end.py
Use non-analytical models for now
2019-07-25 14:55:42 -07:00
config_scn4m_subm_front_end.py
Minor cleanup. Skip more tests until analytical fixed.
2019-07-26 08:33:06 -07:00
config_scn4m_subm.py
Fix space before comment
2019-06-14 08:43:41 -07:00
regress.py
Merge branch 'pep8_cleanup' into dev
2019-06-14 08:47:10 -07:00
sram_1rw_1r_tb.v
Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
2019-01-11 14:15:16 -08:00
sram_1rw_tb.v
Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
2019-01-11 14:15:16 -08:00
sram_1rw_wmask_tb.v
Verified 1rw mask writing and changed verilog.py accordingly.
2019-07-05 15:08:59 -07:00
testutils.py
Merge remote-tracking branch 'origin/dev' into rbl_revamp
2019-07-12 11:10:07 -07:00