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bank.py
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Connect RBL to bottom of precharge cell
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2020-06-04 10:22:52 -07:00 |
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bank_select.py
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Changes to simplify metal preferred directions and pitches.
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2020-05-10 11:32:45 -07:00 |
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bitcell_array.py
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Configured bitline directions into prot_data
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2020-04-20 14:23:40 -07:00 |
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bitcell_base_array.py
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update for end caps
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2020-05-27 20:03:11 -07:00 |
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col_cap_array.py
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update for end caps
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2020-05-27 20:03:11 -07:00 |
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control_logic.py
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Changes to simplify metal preferred directions and pitches.
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2020-05-10 11:32:45 -07:00 |
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delay_chain.py
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Changes to allow decoder height to be a 2x multiple of bitcell height.
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2020-05-10 06:56:22 -07:00 |
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dff_array.py
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add custom module file, make dff clk pin dynamic
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2020-02-04 23:35:06 -08:00 |
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dff_buf.py
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Changes to simplify metal preferred directions and pitches.
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2020-05-10 11:32:45 -07:00 |
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dff_buf_array.py
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Add supply rails to dff array. PEP8 cleanup.
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2020-04-21 15:21:29 -07:00 |
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dff_inv.py
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Clean up and generalize layer rules.
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2019-12-17 11:03:36 -08:00 |
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dff_inv_array.py
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Clean up and generalize layer rules.
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2019-12-17 11:03:36 -08:00 |
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dummy_array.py
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Fix base bitcell syntax error. Remove some unused imports.
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2020-01-30 01:58:30 +00:00 |
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hierarchical_decoder.py
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Variable zjog. 512 port address test. s8 port address working.
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2020-06-04 16:01:32 -07:00 |
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hierarchical_predecode.py
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A port option for correct mirroring in port_data.
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2020-06-02 16:50:07 -07:00 |
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hierarchical_predecode2x4.py
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Thin-cell decoder changes.
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2020-05-29 10:36:07 -07:00 |
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hierarchical_predecode3x8.py
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Thin-cell decoder changes.
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2020-05-29 10:36:07 -07:00 |
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hierarchical_predecode4x16.py
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Thin-cell decoder changes.
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2020-05-29 10:36:07 -07:00 |
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module_type.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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multibank.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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port_address.py
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Variable zjog. 512 port address test. s8 port address working.
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2020-06-04 16:01:32 -07:00 |
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port_data.py
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Fixed offset in port_data
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2020-06-04 16:03:39 -07:00 |
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precharge_array.py
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A port option for correct mirroring in port_data.
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2020-06-02 16:50:07 -07:00 |
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replica_bitcell_array.py
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fix for replica column mirroring over y
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2020-05-28 20:31:21 -07:00 |
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replica_column.py
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lvs fix for regression tests
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2020-05-29 13:50:34 -07:00 |
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row_cap_array.py
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update for end caps
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2020-05-27 20:03:11 -07:00 |
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sense_amp.py
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sense_amp: Allow custom pin names
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2020-02-17 15:20:12 +01:00 |
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sense_amp_array.py
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Changes to simplify metal preferred directions and pitches.
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2020-05-10 11:32:45 -07:00 |
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single_level_column_mux_array.py
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Add port to col mux and simplify route with computation to fix mirror bug.
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2020-06-02 13:57:41 -07:00 |
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tri_gate_array.py
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Clean up and generalize layer rules.
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2019-12-17 11:03:36 -08:00 |
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wordline_driver_array.py
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Thin-cell decoder changes.
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2020-05-29 10:36:07 -07:00 |
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write_driver_array.py
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Changes to simplify metal preferred directions and pitches.
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2020-05-10 11:32:45 -07:00 |
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write_mask_and_array.py
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Check min size inverter.
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2020-05-13 16:54:26 -07:00 |
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