mirror of https://github.com/VLSIDA/OpenRAM.git
466 lines
21 KiB
Python
466 lines
21 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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import debug
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import design
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from tech import drc, spice, cell_properties
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from vector import vector
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from globals import OPTS
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from sram_factory import factory
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class replica_bitcell_array(design.design):
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"""
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Creates a bitcell arrow of cols x rows and then adds the replica
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and dummy columns and rows. Replica columns are on the left and
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right, respectively and connected to the given bitcell ports.
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Dummy are the outside columns/rows with WL and BL tied to gnd.
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Requires a regular bitcell array, replica bitcell, and dummy
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bitcell (Bl/BR disconnected).
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"""
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def __init__(self, cols, rows, left_rbl, right_rbl, bitcell_ports, name):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.column_size = cols
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self.row_size = rows
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self.left_rbl = left_rbl
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self.right_rbl = right_rbl
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self.bitcell_ports = bitcell_ports
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debug.check(left_rbl+right_rbl==len(self.all_ports),"Invalid number of RBLs for port configuration.")
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debug.check(left_rbl+right_rbl==len(self.bitcell_ports),"Bitcell ports must match total RBLs.")
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# Two dummy rows/cols plus replica for each port
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self.extra_rows = 2 + left_rbl + right_rbl
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self.extra_cols = 2 + left_rbl + right_rbl
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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# We don't offset this because we need to align
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# the replica bitcell in the control logic
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#self.offset_all_coordinates()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def add_modules(self):
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""" Array and dummy/replica columns
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d or D = dummy cell (caps to distinguish grouping)
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r or R = replica cell (caps to distinguish grouping)
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b or B = bitcell
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replica columns 1
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v v
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bdDDDDDDDDDDDDDDdb <- Dummy row
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bdDDDDDDDDDDDDDDrb <- Dummy row
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br--------------rb
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br| Array |rb
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br| row x col |rb
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br--------------rb
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brDDDDDDDDDDDDDDdb <- Dummy row
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bdDDDDDDDDDDDDDDdb <- Dummy row
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^^^^^^^^^^^^^^^
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dummy rows cols x 1
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^ dummy columns ^
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1 x (rows + 4)
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"""
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# Bitcell for port names only
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self.cell = factory.create(module_type="bitcell")
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# Bitcell array
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self.bitcell_array = factory.create(module_type="bitcell_array",
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column_offset=1 + self.left_rbl,
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cols=self.column_size,
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rows=self.row_size)
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self.add_mod(self.bitcell_array)
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# Replica bitlines
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self.replica_columns = {}
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for bit in range(self.left_rbl+self.right_rbl):
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# Creating left_rbl
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if bit<self.left_rbl:
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replica_bit = bit+1
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# dummy column
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column_offset = self.left_rbl - bit
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# Creating right_rbl
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else:
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replica_bit = bit+self.row_size+1
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# dummy column + replica column + bitcell colums
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column_offset = self.left_rbl - bit + self.row_size
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self.replica_columns[bit] = factory.create(module_type="replica_column",
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rows=self.row_size,
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left_rbl=self.left_rbl,
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right_rbl=self.right_rbl,
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column_offset=column_offset,
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replica_bit=replica_bit)
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self.add_mod(self.replica_columns[bit])
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# Dummy row
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self.dummy_row = factory.create(module_type="dummy_array",
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column
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column_offset=1 + self.left_rbl,
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mirror=0)
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self.add_mod(self.dummy_row)
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# If there are bitcell end caps, replace the dummy cells on the edge of the bitcell array with end caps.
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try:
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end_caps_enabled = cell_properties.bitcell.end_caps
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except AttributeError:
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end_caps_enabled = False
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# Dummy Row or Col Cap, depending on bitcell array properties
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edge_row_module_type = ("col_cap_array" if end_caps_enabled else "dummy_array")
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self.edge_row = factory.create(module_type=edge_row_module_type,
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column
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column_offset=1 + self.left_rbl,
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mirror=0)
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self.add_mod(self.edge_row)
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# Dummy Col or Row Cap, depending on bitcell array properties
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edge_col_module_type = ("row_cap_array" if end_caps_enabled else "dummy_array")
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self.edge_col_left = factory.create(module_type=edge_col_module_type,
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cols=1,
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column_offset=0,
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rows=self.row_size + self.extra_rows,
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mirror=(self.left_rbl+1)%2)
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self.add_mod(self.edge_col_left)
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self.edge_col_right = factory.create(module_type=edge_col_module_type,
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cols=1,
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# dummy column
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# + left replica column
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# + bitcell columns
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# + right replica column
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column_offset=1 + self.left_rbl + self.column_size + self.right_rbl,
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rows=self.row_size + self.extra_rows,
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mirror=(self.left_rbl+1)%2)
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self.add_mod(self.edge_col_right)
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def add_pins(self):
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self.bitcell_array_wl_names = self.bitcell_array.get_all_wordline_names()
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self.bitcell_array_bl_names = self.bitcell_array.get_all_bitline_names()
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# These are the non-indexed names
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self.dummy_cell_wl_names = ["dummy_"+x for x in self.cell.get_all_wl_names()]
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self.dummy_cell_bl_names = ["dummy_"+x for x in self.cell.get_all_bitline_names()]
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self.dummy_row_bl_names = self.bitcell_array_bl_names
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# A dictionary because some ports may have nothing
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self.rbl_bl_names = {}
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self.rbl_br_names = {}
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self.rbl_wl_names = {}
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# Create the full WL names include dummy, replica, and regular bit cells
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self.replica_col_wl_names = []
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self.replica_col_wl_names.extend(["{0}_bot".format(x) for x in self.dummy_cell_wl_names])
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# Left port WLs (one dummy for each port when we allow >1 port)
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for port in range(self.left_rbl):
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# Make names for all RBLs
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wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.cell.get_all_wl_names()))]
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# Keep track of the pin that is the RBL
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self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]]
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self.replica_col_wl_names.extend(wl_names)
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# Regular WLs
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self.replica_col_wl_names.extend(self.bitcell_array_wl_names)
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# Right port WLs (one dummy for each port when we allow >1 port)
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for port in range(self.left_rbl,self.left_rbl+self.right_rbl):
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# Make names for all RBLs
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wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.cell.get_all_wl_names()))]
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# Keep track of the pin that is the RBL
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self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]]
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self.replica_col_wl_names.extend(wl_names)
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self.replica_col_wl_names.extend(["{0}_top".format(x) for x in self.dummy_cell_wl_names])
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# Left/right dummy columns are connected identically to the replica column
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self.dummy_col_wl_names = self.replica_col_wl_names
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# Per port bitline names
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self.replica_bl_names = {}
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self.replica_wl_names = {}
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# Array of all port bitline names
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for port in range(self.left_rbl+self.right_rbl):
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left_names=["rbl_{0}_{1}".format(self.cell.get_bl_name(x),port) for x in range(len(self.all_ports))]
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right_names=["rbl_{0}_{1}".format(self.cell.get_br_name(x),port) for x in range(len(self.all_ports))]
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# Keep track of the left pins that are the RBL
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self.rbl_bl_names[port]=left_names[self.bitcell_ports[port]]
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self.rbl_br_names[port]=right_names[self.bitcell_ports[port]]
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# Interleave the left and right lists
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bl_names = [x for t in zip(left_names, right_names) for x in t]
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self.replica_bl_names[port] = bl_names
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wl_names = ["rbl_{0}_{1}".format(x,port) for x in self.cell.get_all_wl_names()]
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#wl_names[port] = "rbl_wl{}".format(port)
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self.replica_wl_names[port] = wl_names
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# External pins
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self.add_pin_list(self.bitcell_array_bl_names, "INOUT")
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# Need to sort by port order since dictionary values may not be in order
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bl_names = [self.rbl_bl_names[x] for x in sorted(self.rbl_bl_names.keys())]
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br_names = [self.rbl_br_names[x] for x in sorted(self.rbl_br_names.keys())]
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for (bl_name,br_name) in zip(bl_names,br_names):
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self.add_pin(bl_name,"OUTPUT")
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self.add_pin(br_name,"OUTPUT")
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self.add_pin_list(self.bitcell_array_wl_names, "INPUT")
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# Need to sort by port order since dictionary values may not be in order
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wl_names = [self.rbl_wl_names[x] for x in sorted(self.rbl_wl_names.keys())]
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for pin_name in wl_names:
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self.add_pin(pin_name,"INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_instances(self):
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""" Create the module instances used in this design """
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supplies = ["vdd", "gnd"]
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# Used for names/dimensions only
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self.cell = factory.create(module_type="bitcell")
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.bitcell_array_bl_names + self.bitcell_array_wl_names + supplies)
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# Replica columns
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self.replica_col_inst = {}
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for port in range(self.left_rbl+self.right_rbl):
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self.replica_col_inst[port]=self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port])
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self.connect_inst(self.replica_bl_names[port] + self.replica_col_wl_names + supplies)
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_inst = {}
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for port in range(self.left_rbl+self.right_rbl):
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self.dummy_row_replica_inst[port]=self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row)
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self.connect_inst(self.dummy_row_bl_names + self.replica_wl_names[port] + supplies)
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# Top/bottom dummy rows or col caps
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self.dummy_row_bot_inst=self.add_inst(name="dummy_row_bot",
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mod=self.edge_row)
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self.connect_inst(self.dummy_row_bl_names + [x+"_bot" for x in self.dummy_cell_wl_names] + supplies)
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self.dummy_row_top_inst=self.add_inst(name="dummy_row_top",
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mod=self.edge_row)
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self.connect_inst(self.dummy_row_bl_names + [x+"_top" for x in self.dummy_cell_wl_names] + supplies)
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# Left/right Dummy columns
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self.dummy_col_left_inst=self.add_inst(name="dummy_col_left",
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mod=self.edge_col_left)
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self.connect_inst([x+"_left" for x in self.dummy_cell_bl_names] + self.dummy_col_wl_names + supplies)
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self.dummy_col_right_inst=self.add_inst(name="dummy_col_right",
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mod=self.edge_col_right)
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self.connect_inst([x+"_right" for x in self.dummy_cell_bl_names] + self.dummy_col_wl_names + supplies)
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def create_layout(self):
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self.height = (self.row_size+self.extra_rows)*self.dummy_row.height
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self.width = (self.column_size+self.extra_cols)*self.cell.width
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# This is a bitcell x bitcell offset to scale
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offset = vector(self.cell.width, self.cell.height)
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self.bitcell_array_inst.place(offset=[0,0])
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# To the left of the bitcell array
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for bit in range(self.left_rbl):
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self.replica_col_inst[bit].place(offset=offset.scale(-bit-1,-self.left_rbl-1))
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# To the right of the bitcell array
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for bit in range(self.right_rbl):
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self.replica_col_inst[self.left_rbl+bit].place(offset=offset.scale(bit,-self.left_rbl-1)+self.bitcell_array_inst.lr())
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# Far top dummy row (first row above array is NOT flipped)
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flip_dummy = self.right_rbl%2
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self.dummy_row_top_inst.place(offset=offset.scale(0,self.right_rbl+flip_dummy)+self.bitcell_array_inst.ul(),
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mirror="MX" if flip_dummy else "R0")
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# Far bottom dummy row (first row below array IS flipped)
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flip_dummy = (self.left_rbl+1)%2
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self.dummy_row_bot_inst.place(offset=offset.scale(0,-self.left_rbl-1+flip_dummy),
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mirror="MX" if flip_dummy else "R0")
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# Far left dummy col
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self.dummy_col_left_inst.place(offset=offset.scale(-self.left_rbl-1,-self.left_rbl-1))
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# Far right dummy col
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self.dummy_col_right_inst.place(offset=offset.scale(self.right_rbl,-self.left_rbl-1)+self.bitcell_array_inst.lr())
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# Replica dummy rows
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for bit in range(self.left_rbl):
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self.dummy_row_replica_inst[bit].place(offset=offset.scale(0,-bit-bit%2),
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mirror="R0" if bit%2 else "MX")
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for bit in range(self.right_rbl):
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self.dummy_row_replica_inst[self.left_rbl+bit].place(offset=offset.scale(0,bit+bit%2)+self.bitcell_array_inst.ul(),
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mirror="MX" if bit%2 else "R0")
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self.translate_all(offset.scale(-1-self.left_rbl,-1-self.left_rbl))
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_layout_pins(self):
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""" Add the layout pins """
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# Main array wl and bl/br
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pin_names = self.bitcell_array.get_pin_names()
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for pin_name in pin_names:
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for wl in self.bitcell_array_wl_names:
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if wl in pin_name:
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(0,1),
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width=self.width,
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height=pin.height())
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for bitline in self.bitcell_array_bl_names:
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if bitline in pin_name:
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(1,0),
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width=pin.width(),
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height=self.height)
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# Replica wordlines
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for port in range(self.left_rbl+self.right_rbl):
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inst = self.replica_col_inst[port]
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for (pin_name,wl_name) in zip(self.cell.get_all_wl_names(),self.replica_wl_names[port]):
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# +1 for dummy row
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pin_bit = port+1
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# +row_size if above the array
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if port>=self.left_rbl:
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pin_bit += self.row_size
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pin_name += "_{}".format(pin_bit)
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pin = inst.get_pin(pin_name)
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if wl_name in self.rbl_wl_names.values():
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self.add_layout_pin(text=wl_name,
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layer=pin.layer,
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offset=pin.ll().scale(0,1),
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width=self.width,
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height=pin.height())
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# Replica bitlines
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for port in range(self.left_rbl + self.right_rbl):
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inst = self.replica_col_inst[port]
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for (pin_name, bl_name) in zip(self.cell.get_all_bitline_names(), self.replica_bl_names[port]):
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pin = inst.get_pin(pin_name)
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if bl_name in self.rbl_bl_names or bl_name in self.rbl_br_names:
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name = bl_name
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else:
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name = "rbl_{0}_{1}".format(pin_name, port)
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self.add_layout_pin(text=name,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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width=pin.width(),
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height=self.height)
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# For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps.
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try:
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bitcell_no_vdd_pin = cell_properties.bitcell.no_vdd_via
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except AttributeError:
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bitcell_no_vdd_pin = False
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for pin_name in ["vdd", "gnd"]:
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for inst in self.insts:
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pin_list = inst.get_pins(pin_name)
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for pin in pin_list:
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if not (pin_name == "vdd" and bitcell_no_vdd_pin):
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self.add_power_pin(name=pin_name,
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loc=pin.center(),
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directions=("V", "V"),
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start_layer=pin.layer)
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def get_rbl_wl_name(self, port):
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""" Return the WL for the given RBL port """
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return self.rbl_wl_names[port]
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def get_rbl_bl_name(self, port):
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""" Return the BL for the given RBL port """
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return self.rbl_bl_names[port]
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def get_rbl_br_name(self, port):
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""" Return the BR for the given RBL port """
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return self.rbl_br_names[port]
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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from tech import drc, parameter
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# Dynamic Power from Bitline
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap()
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|
bl_swing = OPTS.rbl_delay_percentage
|
|
freq = spice["default_event_frequency"]
|
|
bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
|
|
|
|
#Calculate the bitcell power which currently only includes leakage
|
|
cell_power = self.cell.analytical_power(corner, load)
|
|
|
|
#Leakage power grows with entire array and bitlines.
|
|
total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
|
|
cell_power.leakage * self.column_size * self.row_size)
|
|
return total_power
|
|
|
|
def gen_bl_wire(self):
|
|
if OPTS.netlist_only:
|
|
height = 0
|
|
else:
|
|
height = self.height
|
|
bl_pos = 0
|
|
bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), height, drc("minwidth_m1"))
|
|
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
|
|
return bl_wire
|
|
|
|
def get_wordline_cin(self):
|
|
"""Get the relative input capacitance from the wordline connections in all the bitcell"""
|
|
#A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
|
|
bitcell_wl_cin = self.cell.get_wl_cin()
|
|
total_cin = bitcell_wl_cin * self.column_size
|
|
return total_cin
|
|
|
|
def graph_exclude_bits(self, targ_row, targ_col):
|
|
"""Excludes bits in column from being added to graph except target"""
|
|
self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
|
|
|
|
def graph_exclude_replica_col_bits(self):
|
|
"""Exclude all replica/dummy cells in the replica columns except the replica bit."""
|
|
|
|
for port in range(self.left_rbl+self.right_rbl):
|
|
self.replica_columns[port].exclude_all_but_replica()
|
|
|
|
def get_cell_name(self, inst_name, row, col):
|
|
"""Gets the spice name of the target bitcell."""
|
|
return self.bitcell_array.get_cell_name(inst_name+'.x'+self.bitcell_array_inst.name, row, col)
|