OpenRAM

History

Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. Unfold hierarchical decoder to improve routability.		2018-03-23 08:13:10 -07:00
..
base	Single bank passing DRC and LVS again.	2018-03-23 08:13:10 -07:00
characterizer	Fixed accidental changes made to analytical delay.	2018-02-28 12:18:41 -08:00
gdsMill	Ignore non-rectangular pins.	2018-02-16 10:24:57 -08:00
modules	Single bank passing DRC and LVS again.	2018-03-23 08:13:10 -07:00
pgates	Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.	2018-03-23 08:12:47 -07:00
router	Fix unit tests to be DRC clean.	2017-06-07 10:29:53 -07:00
tests	Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.	2018-03-23 08:12:47 -07:00
verify	Single bank passing DRC and LVS again.	2018-03-23 08:13:10 -07:00
Makefile	Add Makefile for parallel test execution.	2018-01-22 13:39:07 -08:00
debug.py	Clean up messages.	2018-02-02 12:31:33 -08:00
example_config_freepdk45.py	Fix num words in example.	2018-02-23 12:17:43 -08:00
example_config_scn3me_subm.py	Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library.	2018-02-12 11:22:47 -08:00
gen_stimulus.py	Add utility script gen_stimulus.py to help create simulations for debugging.	2018-02-26 08:54:35 -08:00
globals.py	Add utility script gen_stimulus.py to help create simulations for debugging.	2018-02-26 08:54:35 -08:00
openram.py	Add utility script gen_stimulus.py to help create simulations for debugging.	2018-02-26 08:54:35 -08:00
options.py	Recreate delay chain and RBL to have vertical poly only.	2018-03-23 08:12:47 -07:00
regress.sh	Add regress.sh script for convenience	2016-11-18 08:00:34 -08:00
sram.py	Single bank passing DRC and LVS again.	2018-03-23 08:13:10 -07:00