OpenRAM/compiler/base
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again.
Unfold hierarchical decoder to improve routability.
2018-03-23 08:13:10 -07:00
..
contact.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
design.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
geometry.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
hierarchy_layout.py Single bank passing DRC and LVS again. 2018-03-23 08:13:10 -07:00
hierarchy_spice.py Move label pins to center like layout pins. 2018-03-23 08:12:59 -07:00
lef.py Move last few modules to base dir 2018-02-09 10:29:37 -08:00
path.py Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-02-09 10:25:28 -08:00
pin_layout.py Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array. 2018-03-23 08:12:47 -07:00
route.py Move last few modules to base dir 2018-02-09 10:29:37 -08:00
utils.py Move utils to base. 2018-02-09 10:42:23 -08:00
vector.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
verilog.py Move last few modules to base dir 2018-02-09 10:29:37 -08:00
wire.py Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-02-09 10:25:28 -08:00