mirror of https://github.com/VLSIDA/OpenRAM.git
80 lines
2.7 KiB
Python
80 lines
2.7 KiB
Python
import optparse
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import getpass
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import os
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class options(optparse.Values):
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"""
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Class for holding all of the OpenRAM options. All of these options can be over-riden in a configuration file
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that is the sole required command-line positional argument for openram.py.
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"""
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# This is the technology directory.
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openram_tech = ""
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# This is the name of the technology.
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tech_name = ""
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# This is the temp directory where all intermediate results are stored.
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openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid())
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#openram_temp = "/Users/{}/openram_temp/".format(getpass.getuser())
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# This is the verbosity level to control debug information. 0 is none, 1
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# is minimal, etc.
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debug_level = 0
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# This determines whether LVS and DRC is checked for each submodule.
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check_lvsdrc = True
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# Variable to select the variant of spice
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spice_name = ""
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# Should we print out the banner at startup
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print_banner = True
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# The DRC/LVS/PEX executable being used which is derived from the user PATH.
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drc_exe = None
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lvs_exe = None
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pex_exe = None
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# The spice executable being used which is derived from the user PATH.
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spice_exe = ""
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# Run with extracted parasitics
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use_pex = False
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# Remove noncritical memory cells for characterization speed-up
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trim_netlist = True
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# Use detailed LEF blockages
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detailed_blockages = True
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# Define the output file paths
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output_path = "."
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# Define the output file base name
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output_name = ""
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# Use analytical delay models by default rather than (slow) characterization
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analytical_delay = True
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# Purge the temp directory after a successful run (doesn't purge on errors, anyhow)
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purge_temp = True
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# These are the configuration parameters
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rw_ports = 1
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r_ports = 0
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# These will get initialized by the the file
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supply_voltages = ""
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temperatures = ""
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process_corners = ""
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# These are the default modules that can be over-riden
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decoder = "hierarchical_decoder"
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ms_flop = "ms_flop"
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ms_flop_array = "ms_flop_array"
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dff = "dff"
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dff_array = "dff_buf_array"
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control_logic = "control_logic"
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bitcell_array = "bitcell_array"
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sense_amp = "sense_amp"
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sense_amp_array = "sense_amp_array"
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precharge_array = "precharge_array"
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column_mux_array = "single_level_column_mux_array"
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write_driver = "write_driver"
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write_driver_array = "write_driver_array"
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tri_gate = "tri_gate"
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tri_gate_array = "tri_gate_array"
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wordline_driver = "wordline_driver"
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replica_bitline = "replica_bitline"
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replica_bitcell = "replica_bitcell"
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bitcell = "bitcell"
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delay_chain = "delay_chain"
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bank_select = "bank_select"
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