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bank.py
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Single bank passing DRC and LVS again.
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2018-03-23 08:13:10 -07:00 |
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bank_select.py
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Single bank passing DRC and LVS again.
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2018-03-23 08:13:10 -07:00 |
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bitcell.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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bitcell_array.py
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Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.
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2018-03-23 08:12:47 -07:00 |
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control_logic.py
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Single bank passing DRC and LVS again.
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2018-03-23 08:13:10 -07:00 |
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delay_chain.py
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Recreate delay chain and RBL to have vertical poly only.
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2018-03-23 08:12:47 -07:00 |
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dff.py
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Add dff_buf for buffered flop arrays.
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2018-03-04 16:13:10 -08:00 |
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dff_array.py
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Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.
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2018-03-23 08:12:47 -07:00 |
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dff_buf.py
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Add dff_buf and dff_array modules.
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2018-03-23 08:11:51 -07:00 |
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dff_buf_array.py
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Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.
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2018-03-23 08:12:47 -07:00 |
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hierarchical_decoder.py
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Single bank passing DRC and LVS again.
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2018-03-23 08:13:10 -07:00 |
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hierarchical_predecode.py
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Single bank passing DRC and LVS again.
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2018-03-23 08:13:10 -07:00 |
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hierarchical_predecode2x4.py
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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
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2018-02-26 16:32:28 -08:00 |
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hierarchical_predecode3x8.py
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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
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2018-02-26 16:32:28 -08:00 |
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ms_flop.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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ms_flop_array.py
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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
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2018-02-26 16:32:28 -08:00 |
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precharge.py
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Fix typo in precharge.
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2018-02-12 15:34:01 -08:00 |
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precharge_array.py
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Change precharge input from clk to en
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2018-02-12 15:32:47 -08:00 |
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replica_bitcell.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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replica_bitline.py
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Move label pins to center like layout pins.
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2018-03-23 08:12:59 -07:00 |
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sense_amp.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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sense_amp_array.py
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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
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2018-02-26 16:32:28 -08:00 |
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single_level_column_mux.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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single_level_column_mux_array.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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tri_gate.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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tri_gate_array.py
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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
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2018-02-26 16:32:28 -08:00 |
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wordline_driver.py
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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
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2018-02-26 16:32:28 -08:00 |
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write_driver.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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write_driver_array.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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