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gdsMill
|
Ignore non-rectangular pins.
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2018-02-16 10:24:57 -08:00 |
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modules
|
RBL width is max of delay chain or bitcell load.
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2018-03-05 10:23:13 -08:00 |
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router
|
Fix unit tests to be DRC clean.
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2017-06-07 10:29:53 -07:00 |
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tests
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Move bank select logic to a self contained module.
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2018-03-05 10:22:51 -08:00 |
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Makefile
|
Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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debug.py
|
Clean up messages.
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2018-02-02 12:31:33 -08:00 |
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example_config_freepdk45.py
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Fix num words in example.
|
2018-02-23 12:17:43 -08:00 |
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regress.sh
|
Add regress.sh script for convenience
|
2016-11-18 08:00:34 -08:00 |
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sram.py
|
Add vdd and gnd rails around bank structure.
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2018-03-04 17:53:22 -08:00 |