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base
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All modules have split netlist/layout.
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2018-08-27 11:13:34 -07:00 |
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characterizer
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Edited create_test_cycles to generate values that characterize all ports. Still several bugs and lib file does not support multiple ports.
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2018-08-28 00:30:15 -07:00 |
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gdsMill
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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modules
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Finalized separation of netlist/layout creation.
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2018-08-27 14:18:32 -07:00 |
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pgates
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Finalized separation of netlist/layout creation.
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2018-08-27 14:18:32 -07:00 |
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router
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Fix unit tests to be DRC clean.
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2017-06-07 10:29:53 -07:00 |
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tests
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Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines.
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2018-08-18 15:27:07 -07:00 |
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verify
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Updated to include local magic rules
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2018-08-15 09:46:23 -07:00 |
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Makefile
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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debug.py
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Output debug warnings and errors to stderr. Clean up regress script a bit.
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2018-07-11 09:51:28 -07:00 |
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example_config_freepdk45.py
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Added basic structure to add_test_cycles to characterize multiple ports and its helper functions to allow for ports to be selected for characterization
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2018-08-27 15:56:42 -07:00 |
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example_config_scn3me_subm.py
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Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library.
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2018-02-12 11:22:47 -08:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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globals.py
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Added netlist only configuration option.
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2018-08-27 14:33:02 -07:00 |
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openram.py
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Added netlist only configuration option.
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2018-08-27 14:33:02 -07:00 |
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options.py
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Added netlist only configuration option.
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2018-08-27 14:33:02 -07:00 |
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sram.py
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Added netlist only configuration option.
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2018-08-27 14:33:02 -07:00 |
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sram_1bank.py
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Finalized separation of netlist/layout creation.
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2018-08-27 14:18:32 -07:00 |
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sram_2bank.py
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Add LVS correspondence points to each bank type
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2018-07-18 14:29:04 -07:00 |
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sram_4bank.py
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Add LVS correspondence points to each bank type
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2018-07-18 14:29:04 -07:00 |
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sram_base.py
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Finalized separation of netlist/layout creation.
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2018-08-27 14:18:32 -07:00 |
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