luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
OpenRAM/compiler/modules
History
Bastian Koppelmann 0e641bf905 Remove write_driver_array.py.orig 
this was the remainder of applying a diff using "patch". To avoid this
mistake, add the filetypes created by "patch" to the .gitignore.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 		2020-02-21 13:29:43 +01:00
..
bank.py bank: Connect instances by their individual bl/br names 2020-02-12 15:00:50 +01:00
bank_select.py Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
bitcell_array.py Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
bitcell_base_array.py replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names 2020-02-12 15:37:47 +01:00
control_logic.py Changed layout input names of s_en AND gate to match the schematic 2020-02-19 23:32:11 -08:00
delay_chain.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
dff.py merge custom cell and module properties 2020-02-12 04:09:40 +00:00
dff_array.py add custom module file, make dff clk pin dynamic 2020-02-04 23:35:06 -08:00
dff_buf.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-02-12 06:54:03 +00:00
dff_buf_array.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-02-12 06:54:03 +00:00
dff_inv.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
dff_inv_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
dummy_array.py Fix base bitcell syntax error. Remove some unused imports. 2020-01-30 01:58:30 +00:00
hierarchical_decoder.py Nwell fixes in pgates. 2020-02-06 16:20:09 +00:00
hierarchical_predecode.py Nwell fixes in pgates. 2020-02-06 16:20:09 +00:00
hierarchical_predecode2x4.py Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
hierarchical_predecode3x8.py Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
module_type.py Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
multibank.py Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
port_address.py Add separate well design rules. 2020-01-23 19:43:41 +00:00
port_data.py port_data: Refactor channel_route/connect_bitlines() 2020-02-17 14:20:03 +01:00
precharge_array.py modules/port_data: Add get_bl/br_name method 2020-02-17 14:18:32 +01:00
replica_bitcell_array.py replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names 2020-02-12 15:37:47 +01:00
replica_column.py Bitcell arrays: Allow mirroring on the y axis 2020-01-28 15:51:21 +01:00
sense_amp.py sense_amp: Allow custom pin names 2020-02-17 15:20:12 +01:00
sense_amp_array.py sense_amp: Allow custom pin names 2020-02-17 15:20:12 +01:00
single_level_column_mux_array.py modules/port_data: Add get_bl/br_name method 2020-02-17 14:18:32 +01:00
tri_gate.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
tri_gate_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
wordline_driver.py Pgates are 8 M1 high by default. Port data is bitcell height. 2020-01-30 03:34:04 +00:00
write_driver.py write_driver: Allow custom pin names 2020-02-17 14:25:00 +01:00
write_driver_array.py write_driver: Allow custom pin names 2020-02-17 14:25:00 +01:00
write_mask_and_array.py Move write mask vias to center to avoid data pins. 2019-12-20 11:48:27 -08:00