23 Commits

Author	SHA1	Message	Date
Hunter Nichols	53cb4e7f5e	Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working.	2018-10-22 23:33:01 -07:00
Matt Guthaus	1c426aad29	Merge remote-tracking branch 'origin/datasheet_gen' into supply_routing	2018-10-12 20:55:57 -07:00
Matt Guthaus	5e9fe65907	Remove banks from example configs	2018-10-12 10:23:34 -07:00
Hunter Nichols	7b4e001885	Altered web to only be generated for rw ports.	2018-10-04 15:08:12 -07:00
Hunter Nichols	88f2238e03	Multiport variable bug fix and removed unused code.	2018-10-04 14:09:09 -07:00
Matt Guthaus	2df9b79b28	Remove scn3me lib files. Remove bank references.	2018-09-24 11:28:43 -07:00
Hunter Nichols	8a0411279e	Merge branch 'dev' into multiport_characterization	2018-08-29 01:27:37 -07:00
Matt Guthaus	e17c69be3e	Clean up new code for add_modules, add_pins and netlist/layouts.	2018-08-28 10:24:09 -07:00
Hunter Nichols	350823d434	Added basic structure to add_test_cycles to characterize multiple ports and its helper functions to allow for ports to be selected for characterization	2018-08-27 15:56:42 -07:00
Hunter Nichols	6dc72f5b1e	Added additional control signal to stim file based on # of ports.	2018-08-23 17:46:24 -07:00
Hunter Nichols	efcb435fde	Changed # of address signals to reflect # of ports in delay	2018-08-23 14:49:56 -07:00
Hunter Nichols	9151858449	Characterizer now recognizesmultiple ports and additional DIN/DOUT signals are added to stim file.	2018-08-22 23:45:43 -07:00
Hunter Nichols	8abf45a5d3	Some test code added. To be removed later.	2018-08-22 14:19:09 -07:00
Matt Guthaus	107752b1fb	Fix num words in example.	2018-02-23 12:17:43 -08:00
mguthaus	636099c5e1	Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library.	2018-02-12 11:22:47 -08:00
Matt Guthaus	84b42b0170	Fix bug in trim netlist. Add info comments to spice netlist and trimmed netlist. Increase verbosity for simulations.	2018-02-02 19:33:07 -08:00
Matt Guthaus	490a70dee9	Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.	2018-01-19 16:38:19 -08:00
Matt Guthaus	1701eac1a9	Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells.	2018-01-11 10:24:44 -08:00
Matt Guthaus	9a4b2b4341	Revised LEF and Verilog generation. Does not read GDS for speed improvements.	2017-12-19 09:01:24 -08:00
Matt Guthaus	cf940fb15d	Development version of new pin data structure. Tests pass LVS/DRC except for bank level.	2017-08-23 15:02:15 -07:00
mguthaus	6e90bf0d6d	Enable output filename and path to be in config file. Command line will over-ride config file.	2017-06-12 14:37:15 -07:00
mguthaus	f32912f07c	Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.	2017-06-02 11:11:57 -07:00
Matt Guthaus	e46ff50269	Modified default tech back to freepdk. Config file overrides command line.	2017-01-11 11:47:58 -08:00