 mrg
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f6587badad
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Improve supply routing for ring and side pins
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2021-05-28 10:58:30 -07:00 |
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 Hunter Nichols
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da67edbde8
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Changed input format for delay module in xyce delay test.
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2021-05-26 20:11:30 -07:00 |
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Hunter Nichols
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b3bcf48d2e
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Merge branch 'dev' into automated_analytical_model
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2021-05-26 18:42:24 -07:00 |
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Hunter Nichols
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a53c6c51ed
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Added sim data for freepdk45 and removed stale data
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2021-05-26 18:40:46 -07:00 |
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mrg
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61221ff4fa
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Allow tree type
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2021-05-26 17:46:41 -07:00 |
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mrg
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8bf37ca708
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Connect dnwell taps to gnd
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2021-05-26 17:38:09 -07:00 |
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mrg
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2b5013fd69
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Config example changes
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2021-05-26 16:14:48 -07:00 |
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mrg
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7736d3b927
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Fix updated side pin option
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2021-05-26 16:14:46 -07:00 |
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mrg
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6de5787e58
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Fix offsets for ring
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2021-05-26 16:14:16 -07:00 |
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mrg
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e611f66767
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Add dnwell
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2021-05-26 16:14:16 -07:00 |
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mrg
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6493d1a7f4
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Add dnwell
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2021-05-26 16:14:16 -07:00 |
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mrg
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cc91cdf008
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Add power ring pin
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2021-05-26 16:14:14 -07:00 |
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mrg
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bc793ec3d8
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PEP8
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2021-05-26 16:13:47 -07:00 |
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mrg
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8610144ccb
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Fix write size warning
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2021-05-26 16:13:47 -07:00 |
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mrg
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e16f44cc81
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Update lib file with external supply names
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2021-05-26 15:34:32 -07:00 |
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mrg
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d579a60382
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Fix external supply names in verilog
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2021-05-26 15:26:20 -07:00 |
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mrg
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7fa6c7ce0f
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Typo in wmask supply variable
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2021-05-26 15:24:31 -07:00 |
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mrg
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4a8e0cdabb
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Add top-level pin functionality
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2021-05-26 15:04:52 -07:00 |
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Hunter Nichols
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2f4f8ca912
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Fixed conflicts in delay and elmore modules on merge with dev.
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2021-05-25 15:25:43 -07:00 |
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Hunter Nichols
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52bf8d09d7
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Added tech dir to model output so different tech dont overwrite the outputs of eachother.
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2021-05-25 15:21:32 -07:00 |
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Hunter Nichols
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76f5578cc1
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Removed path delays from characterization output to not disturb the current testing flow.
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2021-05-25 15:19:27 -07:00 |
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Hunter Nichols
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23368c0fcf
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Updated tests and elmore model with load_slew lists. Changed naming on characterization output to not clash with testing.
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2021-05-25 14:49:28 -07:00 |
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Hunter Nichols
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1488b31dce
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Adjusted model prediction to account for a single datafile. Adjusted unscaling data as well.
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2021-05-24 12:53:51 -07:00 |
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Hunter Nichols
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53503f40d2
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Changed util functions to expect multiple outputs in data. Changed train models to account for multiple outputs when reading in data.
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2021-05-24 12:03:26 -07:00 |
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Hunter Nichols
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a4cb539f72
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Removed old sim data csvs and added a new version. Added a default check for LAS in data extraction.
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2021-05-24 10:44:46 -07:00 |
|
 Jesse Cirimelli-Low
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f9eae3fb80
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route bias pisn
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2021-05-24 02:42:04 -07:00 |
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mrg
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9c01e22281
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Prioritize Xyce.
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2021-05-21 12:05:10 -07:00 |
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mrg
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f856a44376
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Restrict to direct KLU solver
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2021-05-21 12:04:26 -07:00 |
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mrg
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fc17a1ff45
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Xyce can be capital or lower case
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2021-05-21 12:04:26 -07:00 |
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mrg
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d51ec4fe45
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Add Xyce tests
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2021-05-21 12:04:26 -07:00 |
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mrg
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1274824793
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Restrict to direct KLU solver
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2021-05-21 11:27:15 -07:00 |
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mrg
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eadf7eedc5
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Prioritize Xyce to last until bugs resolved.
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2021-05-21 10:01:37 -07:00 |
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Hunter Nichols
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4e40017fdc
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Added model configs adapted from OpenRAM Library
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2021-05-20 15:26:24 -07:00 |
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Hunter Nichols
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41c8eeb23c
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Adjusted paths in makefile for generating data used in regression models
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2021-05-20 13:05:16 -07:00 |
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Hunter Nichols
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269b698b0a
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Fixed issues with csv generation. Added regex parsing to determine corners from datasheet.
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2021-05-18 23:41:16 -07:00 |
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mrg
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38322dae4e
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Xyce can be capital or lower case
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2021-05-18 14:58:57 -07:00 |
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mrg
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7c001732b1
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Add destination file as dot file
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2021-05-18 14:54:13 -07:00 |
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mrg
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191b382171
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Change magic to use OPENRAM_MAGICRC if defined.
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2021-05-18 13:27:11 -07:00 |
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Hunter Nichols
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36b1bc1284
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Added script to extract data from datasheet output and store in CSV.
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2021-05-17 14:04:20 -07:00 |
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Hunter Nichols
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0434e57609
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Added target in makefile to run configs and store results in tech directory.
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2021-05-17 14:03:32 -07:00 |
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mrg
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1a2865b9b1
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Add Xyce tests
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2021-05-14 17:07:00 -07:00 |
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mrg
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3abebe4068
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Add hierarchical seperator option to work with Xyce measurements.
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2021-05-14 16:16:25 -07:00 |
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mrg
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7534610cdd
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Add MPI capability for Xyce threading.
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2021-05-14 11:45:37 -07:00 |
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mrg
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507ad9f33d
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Change sim threads to 3.
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2021-05-14 11:45:10 -07:00 |
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mrg
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67a67111a6
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Initial Xyce support.
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2021-05-14 11:28:29 -07:00 |
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mrg
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3959cf73d1
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Remove setup/hold measure and compute it directly.
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2021-05-14 10:11:14 -07:00 |
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mrg
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9555b52aaa
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Remove setup/hold measure and compute it directly.
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2021-05-14 10:01:10 -07:00 |
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Jesse Cirimelli-Low
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0ba229afe5
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Merge branch 'dev' into laptop_checkpoint
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2021-05-07 19:06:17 -07:00 |
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Jesse Cirimelli-Low
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e5662180e8
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single port 20 series tests running
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2021-05-07 18:44:45 -07:00 |
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Jesse Cirimelli-Low
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6d8411d19f
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use consistent amp spacing
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2021-05-07 11:29:43 -07:00 |
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