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OpenRAM
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134 Commits

Author SHA1 Message Date
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
Matt Guthaus 4b1c359089 update copyright year. 2021-01-22 11:24:53 -08:00
Hunter Nichols c8e631108a Updated sim_data for scmos 2021-01-22 00:51:14 -08:00
Hunter Nichols 59200d1048 Added updated data for scmos, removed unused files. 2021-01-13 13:09:21 -08:00
Hunter Nichols d6177b34f0 Added data which includes corner as an input feature 2020-12-17 12:59:06 -08:00
Hunter Nichols f1f6a1a520 Removed windows end of line characters. 2020-12-15 12:08:31 -08:00
Hunter Nichols 06232dee8f Added leakage and slew data. Added temporary fix to model output format. 2020-12-14 14:32:10 -08:00
Hunter Nichols 25544c3974 Added similar interface to linear regression as elmore 2020-12-14 13:59:31 -08:00
Hunter Nichols b1a7e0e55b Added power data 2020-12-09 15:21:22 -08:00
Hunter Nichols 1143dbec94 Added initial scripts and data to generate analytical model 2020-11-20 12:40:04 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg a2f29e5edd Fix missing nand4_leakage #97 2020-11-12 09:48:08 -08:00
mrg 66633a843b Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
mrg 423e2c165f Remove test cell in scn4m_subm tech.py 2020-11-03 16:38:55 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg 87419bd640 Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg ef310970bf Use new Google PDK lib 2020-10-12 15:46:11 -07:00
mrg 71d86f88b0 Merge branch 'dev' into wlbuffer 2020-09-10 13:05:14 -07:00
mrg 138cbfac15 Flatten dummy pbitcell too 2020-09-09 12:58:22 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
mrg dfb593e9b4 Add draft lyt file -- connectivity not working 2020-08-14 10:38:22 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg a989ea63a0 Move magic/netgen files to tech dir 2020-07-09 11:33:14 -07:00
mrg cddb16dabc Separate active and poly contact to gate rule 2020-06-24 09:17:39 -07:00
mrg e69b665689 Flatten pbitcell_1 too 2020-06-02 09:31:43 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg 5f76514cf0 Remove end of line whitespace 2020-04-21 15:20:51 -07:00
Jesse Cirimelli-Low aedbc5f968 merge custom cell and module properties 2020-02-12 04:09:40 +00:00
Jesse Cirimelli-Low 18573c0e42 add module properties to other technologies 2020-02-05 22:25:35 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
Matt Guthaus 3147b99ce0 Merge remote-tracking branch 'bkoppelmann/bit-sym' into dev 2020-01-29 11:24:09 -08:00
Bastian Koppelmann df9f351a91 Add custom cell properties to technologies 
this is technology specific database to store data about the custom
design cells. For now it only contains on which axis the bitcells are
mirrored. This is a first step to support thin cells that need to be
mirrored on the x and y axis.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:46:14 +01:00
Bastian Koppelmann 407bd026ee tech: Make m3_stack the power_grid stack for FreePDK45/scn4m 
explicitly stating the power_grid makes people porting a new technology
aware of this option.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 12:06:38 +01:00
Jesse Cirimelli-Low 30604fb093 add multiport support for pex labels 2020-01-28 00:28:55 +00:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
Jesse Cirimelli-Low 2733c3bf3f fix custom bitcell labeling; fix gds scaling in labeling 2020-01-15 09:00:02 +00:00
Jesse Cirimelli-Low 3ab99d7f9c update gds library, generalize geometry reverse transform function 2019-12-24 05:01:55 +00:00
Jesse Cirimelli-Low 5b44dce50d added labels to scn4m magic libaries 2019-12-23 02:22:11 +00:00
Matt Guthaus a8d370ee8c Improved comments in tech files 2019-12-20 16:35:31 -08:00
Matt Guthaus b7d78ec2ec Fix ptx active contact orientation to non-default M1 direction. 2019-12-19 12:54:10 -08:00
jcirimel f0958b0b11 squashed update of pex progress due to timezone error 2019-12-18 03:03:13 -08:00
Matthew Guthaus 8e151553e4 Update contact types. 
Use preferred directions in tech files.
Programmatically generate based on interconnect stacks.
 2019-12-17 23:45:07 +00:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Bastian Koppelmann 1380cbc50c technology: Add tech_module to all technologies 
this allows each technology to override each cell class.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-16 16:51:41 +01:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Matt Guthaus e048ada23c Abstract basic DRC checks 2019-12-11 17:56:55 -08:00