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OpenRAM
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201 Commits

Author SHA1 Message Date
samuelkcrow dfbf0ba6e1 Make git dependency visible and enforce it. 
resolves #87
 2021-10-04 14:43:14 -07:00
mrg 6f4d9f17af v1.1.18 2021-08-18 11:30:00 -07:00
mrg e88f927e01 v1.1.17 2021-07-29 11:41:41 -07:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
mrg d6d0df97f8 Get rid of write_size error when write_size==word_size 2021-05-28 13:06:12 -07:00
mrg bc793ec3d8 PEP8 2021-05-26 16:13:47 -07:00
mrg 8610144ccb Fix write size warning 2021-05-26 16:13:47 -07:00
mrg 3abebe4068 Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
Jesse Cirimelli-Low d3199ea70e Merge branch 'dev' into laptop_checkpoint 2021-05-03 12:53:31 -07:00
Jesse Cirimelli-Low 3a3da9e0d7 56 drc errors on col mux 1port 2021-05-02 21:49:09 -07:00
mrg d018963866 Specify ImportError to see other errors 2021-04-22 16:13:32 -07:00
mrg 9b40102bbb v1.1.15 2021-04-19 11:54:35 -07:00
mrg aa5e1fd168 Merge remote-tracking branch 'olofk/verilog_model_features' into dev 2021-04-15 14:41:56 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
mrg 506daaec99 Merge remote-tracking branch 'private/dev' into dev 2021-02-13 23:52:18 -08:00
mrg 7610f23fc7 Sub temp directory. Add github archive. 2021-02-10 15:39:12 -08:00
mrg c78d3a9cca Merge branch 'dev' into runner_test 2021-02-10 11:17:35 -08:00
mrg 29c3d46be6 Warn about threads forced to 1 2021-02-10 10:23:06 -08:00
mrg b83d93cc9a GitHub Actions CI flow. 2021-02-08 15:46:02 -08:00
mrg 19e99d1c7b Enable parallel regression testing. 2021-02-03 14:19:11 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg f428ff4bfd v1.1.14 2021-01-07 10:33:21 -08:00
mrg 81220068f7 v1.1.13 2020-12-23 11:59:54 -08:00
mrg 80c0bccd70 Merge remote-tracking branch 'private/dev' into dev 2020-12-23 11:59:38 -08:00
mrg fc91c0da23 Only warn if characterizing. 2020-12-21 12:44:37 -08:00
mrg bcd837205b v1.1.12 2020-12-18 13:05:42 -08:00
mrg 0bd169708c v1.1.11 2020-12-15 14:38:54 -08:00
mrg 028d2a2954 v1.1.10 2020-12-15 10:56:45 -08:00
mrg b5e532940c v1.1.9 2020-12-08 12:05:30 -08:00
mrg 971f2ac114 v1.1.8 2020-12-08 10:50:35 -08:00
mrg ebe19abf60 Merge remote-tracking branch 'private/dev' into dev 2020-12-08 10:50:02 -08:00
Arya Reais-Parsi 9eb2f3c0e6 add error message when configuration files are not valid python module names 2020-12-08 10:43:29 -08:00
mrg edf3d9557d Purge temp at the start of every run if it exists. 2020-12-02 11:09:40 -08:00
mrg 0250d9add7 v1.1.7 2020-12-01 17:15:03 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg 0ba2feee53 Fix errors in new run_sim calls and corners 2020-11-09 13:59:46 -08:00
mrg 493c9125f1 Read different modules overrides for different num ports 2020-11-06 11:09:50 -08:00
mrg 18d2987805 Cleanup 2020-11-05 16:30:15 -08:00
mrg 2c76a2680f Adjust openram options. 
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
 2020-11-05 13:12:26 -08:00
mrg 3315fe32ba Improve nominal corner message 2020-11-03 16:49:49 -08:00
mrg 45cdecdea9 Improve error message about missing DRC/LVS tools. 2020-11-03 15:47:04 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg 87419bd640 Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg f9787eb878 Use bitcell_base for all bitcells. Fix missing setup_bitcell call 2020-11-02 17:00:15 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
mrg 1caecf5a69 Undo version and traceback 2020-11-02 10:44:49 -08:00
Tim 'mithro' Ansell 232f754c73 Adding traceback printing to tech file import. 2020-11-02 09:52:00 -08:00
mrg 5268ec547b Merge remote-tracking branch 'private/dev' into dev 2020-10-16 16:51:50 -07:00