14 Commits

Author	SHA1	Message	Date
Jesse Cirimelli-Low	88241ca685	add fix for cypress sp wls	2026-04-28 17:19:54 -07:00
Jesse Cirimelli-Low	515591a422	dual port rba lvs clean again with cell library changes	2026-04-14 14:48:26 -07:00
Jesse Cirimelli-Low	5a74605117	single port fixes	2025-09-12 11:25:03 -07:00
Jesse Cirimelli-Low	f3c1c5fbb2	Merge branch 'singleport_refactor' into array_gen	2025-02-24 23:26:28 -08:00
Jesse Cirimelli-Low	d7c3bbea3e	crba passing again norbl/leftrbl	2023-10-28 18:05:07 -07:00
Jesse Cirimelli-Low	72a7b0342b	work on capped rba	2023-08-25 16:39:32 -07:00
Jesse Cirimelli-Low	036cc54b99	rba done w/o wordline	2023-08-24 02:55:45 -07:00
Jesse Cirimelli-Low	f890160601	add nwell routing in bca	2023-08-21 20:12:36 -07:00
Jesse Cirimelli-Low	5a6c78865d	singleport bitcell array laying out	2023-08-21 19:24:06 -07:00
Eren Dogan	e5fc25da6f	Update copyright year	2023-01-28 22:56:27 -08:00
Eren Dogan	96e57507bf	Add copyright check to code format test	2022-11-30 14:50:43 -08:00
Eren Dogan	fccdc3c45b	Use library imports globally	2022-11-27 13:01:20 -08:00
Jesse Cirimelli-Low	3b02a8846d	sky130 rba passing :)	2022-09-12 16:07:00 -07:00
mrg	d92c7a634d	Use packages for imports. ... Must set PYTHONPATH to include OPENRAM_HOME now. Reorganizes subdirs as packages. Rewrites unit tests to use packages. Update README.md with instructions, dependencies etc. Update sky130 module imports. Change tech specific package from modules to custom.	2022-07-13 15:55:57 -07:00