14 Commits

Author	SHA1	Message	Date
Matt Guthaus	d99dcd33e2	Fix SRAM level control routing errors.	2018-11-28 15:30:52 -08:00
Matt Guthaus	c45f990413	Change en to en_bar in precharge. Fix logic for inverted p_en_bar.	2018-11-27 14:17:55 -08:00
Matt Guthaus	ce8c2d983d	Update all drc usages to call function type	2018-10-12 14:37:51 -07:00
Matt Guthaus	e22e658090	Converted all submodules to use _bit notation instead of [bit]	2018-10-11 09:53:08 -07:00
Matt Guthaus	e17c69be3e	Clean up new code for add_modules, add_pins and netlist/layouts.	2018-08-28 10:24:09 -07:00
Matt Guthaus	6401cbf2a6	Move place function to instance class rather than hierarchy.	2018-08-27 17:25:39 -07:00
Matt Guthaus	8664f7a0b8	Converted all modules to not run create_layout when netlist_only ... mode is enabled.	2018-08-27 16:42:48 -07:00
Matt Guthaus	87f539f3a8	Separate netlist/layout for flop and precharge array.	2018-08-27 10:54:21 -07:00
Michael Timothy Grimes	0f8da1510e	Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines.	2018-08-18 15:27:07 -07:00
Michael Timothy Grimes	040340b49f	editted naming convention on precharge to accommodate multiport	2018-08-15 02:14:45 -07:00
Michael Timothy Grimes	8d97862f6e	altered precharge array and precharge unit tests to accommodate multiport	2018-08-15 00:55:23 -07:00
Matt Guthaus	a772217172	Route precharge_array vdd in M3	2018-04-04 13:49:55 -07:00
Matt Guthaus	e32b0b8f7a	Change precharge input from clk to en	2018-02-12 15:32:47 -08:00
Matt Guthaus	7100d6f904	Organize top-level files into subdirs.	2018-02-09 10:25:24 -08:00